CMOS Counter/Dividers

Features: Fully static operation = Medium-speed operation . . 10 MHz (typ) at Vpp = 10 V Standardized, symmetrical output characteristics 100% tested for quiescent current at 20 V 5-V,10V, and 15-V parametric ratings Meets all requirements of JEDEC Tentative Standard No. 134, “St

文件：1.01958 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

CMOS Counter/Dividers

文件：1.03167 Mbytes 頁數(shù)：19 Pages

TI

德州儀器

具有 8 個解碼輸出的 CMOS 十進(jìn)制計(jì)數(shù)器

CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall time ? Fully static operation\n? Medium speed operation…10 MHz (typ.) at VDD = 10 V\n? Standardized, symmetrical output characteristics\n? 100% tested for quiescent current at 20 V\n? 5-V, 10-V, and 15-V parametric ratings\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Spec;

TI

德州儀器

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes 頁數(shù)：8 Pages

NSC

國半

Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

文件：165.76 Kbytes 頁數(shù)：8 Pages

NSC

國半

CMOS Counter/Dividers

CD4017BMS and CD4022BMS are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fal

文件：157.83 Kbytes 頁數(shù)：10 Pages

INTERSIL