CMOS Dual 4-Stage Static Shift Register

Features: ? Medium speed operation . ............ 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ? Fully static operation ? 8 master-slave flip-flops plus input and output buffering ? 100% tested for quiescent current at 20 V ?5.V, 10-V, and 15-V parametric ratings ? Standardized, symmetr

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TI

德州儀器

CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation ............. 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ? Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

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TI

德州儀器

CMOS Dual 4-stage Static Shift Register

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德州儀器

CMOS 雙路 4 級(jí)靜態(tài)移位寄存器

CD4015B consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. \"Q\"outputs are available from each of the four stages on both registers. All register stages are D-type,master ? Medium speed operation...12 MHz (typ.) clock rate at VDD ? VSS = 10 V\n? 8 master-slave flip-flops plus input and output buffering\n? 5-V, 10-V, and 15-V parametric ratings\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? 2 V at VDD = 10 V\n?;

TI

德州儀器