絲?。?a target="_blank" title="Marking" href="/cd40147be/marking.html">CD40147BE；Package：PDIP；null10-Line to 4-Line BCD Priority Encoder

Features: ? Encodes 10-ine to 4-line BCD ? Active low inputs and outputs ? Standardized, symmetrical output characteristics ? 100% tested for quiescent current at 20 V ?5-V, 10-V, and 15-V parametric ratings ? Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

文件：398.38 Kbytes 頁數(shù)：8 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd40147bm/marking.html">CD40147BM；Package：SOIC；null10-Line to 4-Line BCD Priority Encoder

Features: ? Encodes 10-ine to 4-line BCD ? Active low inputs and outputs ? Standardized, symmetrical output characteristics ? 100% tested for quiescent current at 20 V ?5-V, 10-V, and 15-V parametric ratings ? Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

文件：398.38 Kbytes 頁數(shù)：8 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd40147bm/marking.html">CD40147BM；Package：SOIC；null10-Line to 4-Line BCD Priority Encoder

Features: ? Encodes 10-ine to 4-line BCD ? Active low inputs and outputs ? Standardized, symmetrical output characteristics ? 100% tested for quiescent current at 20 V ?5-V, 10-V, and 15-V parametric ratings ? Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

文件：398.38 Kbytes 頁數(shù)：8 Pages

TI

德州儀器

10 Line to 4 Line BCD Priority Encoder

Description CD40147BMS CMOS encoder features priority encoding of the inputs to ensure that only the highest order data line is encoded. Ten data input lines (0-9) are encoded to four line (8,4, 2, 1) BCD. The highest priority line is line 9. All four output lines are logic 1 (VSS) when all input

文件：81.23 Kbytes 頁數(shù)：8 Pages

INTERSIL

CMOS 8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The UTC CD4014 isa 8-stage synchronous parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and individual parallel inputs to each register stage. Each register is a D-type master-slave flip-flop. Q6, Q7, and Q

文件：216.27 Kbytes 頁數(shù)：9 Pages

UTC

友順

8-Stage Static Shift Register

General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabili

文件：67.34 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

8-Stage Static Shift Register

General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabili

文件：67.34 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

8-Stage Static Shift Register

General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabili

文件：67.34 Kbytes 頁數(shù)：7 Pages

FAIRCHILD

仙童半導(dǎo)體

CMOS 8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The UTC CD4014 isa 8-stage synchronous parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and individual parallel inputs to each register stage. Each register is a D-type master-slave flip-flop. Q6, Q7, and Q

文件：216.27 Kbytes 頁數(shù)：9 Pages

UTC

友順

CMOS 8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The UTC CD4014 isa 8-stage synchronous parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and individual parallel inputs to each register stage. Each register is a D-type master-slave flip-flop. Q6, Q7, and Q

文件：216.27 Kbytes 頁數(shù)：9 Pages

UTC

友順