CMOS 8-stage Presettable Synchronous Down Counters

文件：1.20375 Mbytes 頁數(shù)：17 Pages

TI

德州儀器

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

CMOS 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

文件：572.14 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

CMOS 8 級可預(yù)置 8 位二進(jìn)制同步遞減計(jì)數(shù)器

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enablin ? Synchronous or asynchronous preset\n? Cascadable\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Standardized, symmetrical output characteristics\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for De;

TI

德州儀器

CMOS 8 級可預(yù)置 8 位二進(jìn)制同步遞減計(jì)數(shù)器

CD40102B, and CD40103B consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102B is configured as two cascaded 4-bit BCD counters, and the CD40103B contains a single 8-bit binary counter. Each type has control inputs for enablin ? Synchronous or asynchronous preset\n? Cascadable\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Standardized, symmetrical output characteristics\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for De;

TI

德州儀器

CMOS 8-Stage Presettable Synchronous Down Counters

Renesas

瑞薩

Package：16-DIP（0.300"，7.62mm）；包裝：管件 類別：集成電路（IC） 計(jì)數(shù)器，除法器 描述：IC SYNC DOWN COUNTER 8STG 16-DIP

TI

德州儀器

Package：16-SOIC（0.209"，5.30mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 計(jì)數(shù)器，除法器 描述：IC COUNTER BIN 8BIT CMOS 16SO

TI

德州儀器

Package：16-SOIC（0.209"，5.30mm 寬）；包裝：管件 類別：集成電路（IC） 計(jì)數(shù)器，除法器 描述：IC SYNC DOWN COUNTR 8STG 16SO

TI

德州儀器