ECL/PECL ?1, ?2 Clock Generation Chip with Selectable Enable

文件：106.99 Kbytes 頁數(shù)：7 Pages

AZM

ECL/PECL ?1, ?2 Clock Generation Chip with Selectable Enable

文件：106.99 Kbytes 頁數(shù)：7 Pages

AZM

ECL/PECL ?1, ?2 Clock Generation Chip with Selectable Enable

文件：119.66 Kbytes 頁數(shù)：7 Pages

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PECL/ECL ÷1, ÷2 Clock Generation Chip with Selectable Enable

Arizona

PECL/ECL Clock Generator w/ Divider & Enable

The AZP92 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or Pierce based oscillators. Features are incorporated to reduce board components. A voltage reference and input biasing allows for easy oscillator interface. ? Selectable divide ratio\n? Up to 3.0GHz operation\n?3.3V – 5V analog supply;

Arizona