5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)

Functional description The AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Features

文件：116.77 Kbytes 頁數(shù)：9 Pages

ALSC

5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)

Functional description The AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Features

文件：116.77 Kbytes 頁數(shù)：9 Pages

ALSC

5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)

Functional description The AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Features

文件：116.77 Kbytes 頁數(shù)：9 Pages

ALSC

5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)

Functional description\nThe AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. ? AS7C1024A (5V version)\n? Industrial and commercial temperatures\n? High speed\n? Low power consumption: ACTIVE\n? Low power consumption: STANDBY\n? Latest 6T 0.25u CMOS technology\n? TTL/LVTTL-compatible, three-state I/O\n? ESD protection ≥ 2000 volts\n? Latch-up current ≥ 200 mA?;

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