AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：5.89083 Mbytes 頁數(shù)：244 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：6.21298 Mbytes 頁數(shù)：260 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：6.25469 Mbytes 頁數(shù)：263 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-cor

文件：5.17167 Mbytes 頁數(shù)：265 Pages

TI

德州儀器

AM64x Sitara Processors

文件：5.00627 Mbytes 頁數(shù)：237 Pages

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德州儀器

AM64x Sitara??Processors

文件：5.77773 Mbytes 頁數(shù)：235 Pages

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德州儀器

單核 64 位 Arm? Cortex?-A53，四核 Cortex-R5F，具有 PCIe、USB 3.0 和安全性

AM64x 是 Sitara 新增的工業(yè)級異構 Arm 處理器產(chǎn)品系列，專為要求獨特結合實時處理和通信與應用處理的電機驅(qū)動器和可編程邏輯控制器 (PLC) 等工業(yè)應用而構建。AM64x 將兩個支持 TSN 技術的 Sitara 千兆位 PRU-ICSSG 實例與最多兩個 Arm Cortex-A53 內(nèi)核、最多四個 Cortex-R5F MCU 和一個 Cortex-M4F MCU 合并到一起。\n\nAM64x 旨在通過高性能 R5F 內(nèi)核、緊密耦合的存儲器組、可配置的 SRAM 分區(qū)和進出外設的專用低延遲路徑提供出色的實時性能，從而實現(xiàn)數(shù)據(jù)快速進出 SoC。這種確定性架構允許 AM64x 處理器內(nèi)核： \n? 雙核 Cortex-A53 集群（具有 256KB L2 共享緩存，包括 SECDED ECC）\n? 最多 2 個雙核 Arm Cortex-R5F MCU 子系統(tǒng)，工作頻率高達 800MHz，集成用于實現(xiàn)實時處理 \n? 每個 R5F 內(nèi)核 32KB ICache、32KB DCache 和 64KB TCM，總共 256KB TCM，所有存儲器上都有 SECDED ECC\n? 1 個單核 Arm Cortex-M4F MCU，高達 400MHz \n? 2 個千兆位工業(yè)通信子系統(tǒng) (PRU_ICSSG) \n? 向后兼容 10/100Mb PRU_ICSS\n?;

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：5.89083 Mbytes 頁數(shù)：244 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：6.21298 Mbytes 頁數(shù)：260 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：5.89083 Mbytes 頁數(shù)：244 Pages

TI

德州儀器