AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：5.89083 Mbytes 頁(yè)數(shù)：244 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：6.21298 Mbytes 頁(yè)數(shù)：260 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：6.25469 Mbytes 頁(yè)數(shù)：263 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-cor

文件：5.17167 Mbytes 頁(yè)數(shù)：265 Pages

TI

德州儀器

AM64x Sitara Processors

文件：5.00627 Mbytes 頁(yè)數(shù)：237 Pages

TI

德州儀器

AM64x Sitara??Processors

文件：5.77773 Mbytes 頁(yè)數(shù)：235 Pages

TI

德州儀器

雙核 64 位 Arm? Cortex?-A53，單核 Cortex-R5F，具有 PCIe、USB 3.0 和安全性

AM64x 是 Sitara? 新增的工業(yè)級(jí)異構(gòu) Arm? 處理器產(chǎn)品系列，專為要求獨(dú)特結(jié)合實(shí)時(shí)處理和通信與應(yīng)用處理的電機(jī)驅(qū)動(dòng)器和可編程邏輯控制器 (PLC) 等工業(yè)應(yīng)用而構(gòu)建。AM64x 將兩個(gè)支持 TSN 技術(shù)的 Sitara 器件千兆位 PRU-ICSSG 實(shí)例與最多兩個(gè) Arm? Cortex?-A53 內(nèi)核、最多四個(gè) Cortex-R5F MCU 和一個(gè) Cortex-M4F MCU 合并到一起。\n\nAM64x 旨在通過(guò)高性能 R5F 內(nèi)核、緊密耦合的存儲(chǔ)器組、可配置的 SRAM 分區(qū)和進(jìn)出外設(shè)的專用低延遲路徑提供出色的實(shí)時(shí)性能，從而實(shí)現(xiàn)數(shù)據(jù)快速進(jìn)出 SoC。這種確定性架構(gòu)允許 處理器內(nèi)核： \n? 雙核 Cortex-A53 集群（具有 256KB L2 共享緩存，包括 SECDED ECC）\n? 最多 2 個(gè)雙核 Arm Cortex-R5F MCU 子系統(tǒng)，工作頻率高達(dá) 800MHz，集成用于實(shí)現(xiàn)實(shí)時(shí)處理 \n? 每個(gè) R5F 內(nèi)核 32KB ICache、32KB DCache 和 64KB TCM，總共 256KB TCM，所有存儲(chǔ)器上都有 SECDED ECC\n? 1 個(gè)單核 Arm Cortex-M4F MCU，高達(dá) 400MHz \n? 2 個(gè)千兆位工業(yè)通信子系統(tǒng) (PRU_ICSSG) \n? 向后兼容 10/100Mb PRU_ICSS\n?;

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：5.89083 Mbytes 頁(yè)數(shù)：244 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：5.89083 Mbytes 頁(yè)數(shù)：244 Pages

TI

德州儀器

AM64x Sitara? Processors

1 Features Processor cores: ? 1× Dual 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.0 GHz – Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Up to 2× Dual-co

文件：6.21298 Mbytes 頁(yè)數(shù)：260 Pages

TI

德州儀器