AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：3.64225 Mbytes 頁數(shù)：164 Pages

TI

德州儀器

AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 頁數(shù)：167 Pages

TI

德州儀器

具有實(shí)時(shí)控制和安全功能且頻率高達(dá) 400MHz 的雙核 Arm? Cortex?-R5F MCU

AM263x Sitara? Arm? 微控制器旨在滿足下一代工業(yè)和汽車嵌入式產(chǎn)品復(fù)雜的實(shí)時(shí)處理需求。AM263x MCU 系列由多個(gè)引腳對(duì)引腳兼容器件組成，具有多達(dá)四個(gè) 400-MHz Arm? Cortex?-R5F 內(nèi)核。對(duì)于不同的功能安全配置，可以選擇將多個(gè) Arm? 內(nèi)核編程為在鎖步選項(xiàng)中運(yùn)行。工業(yè)通信子系統(tǒng) (ICSS) 支持集成工業(yè)以太網(wǎng)通信，例如 PROFINET IRT、TSN 或 EtherCAT?（以及許多其他工業(yè)以太網(wǎng)），或用于標(biāo)準(zhǔn)以太網(wǎng)連接或自定義 I/O 接口。該系列設(shè)計(jì)用于先進(jìn)的電機(jī)控制和帶有先進(jìn)模擬模塊的數(shù)字電源控制應(yīng)用。\n\n多個(gè) R5F 內(nèi)核以 256KB 處理器內(nèi)核： \n? 16KB 指令緩存，每個(gè) CPU 內(nèi)核具有 64 位 ECC\n? 64KB 緊耦合存儲(chǔ)器 (TCM)，每個(gè) R5F 內(nèi)核具有 32 位 ECC\n? 2MB 片上 RAM (OCSRAM) \n? ECC 錯(cuò)誤保護(hù)\n? 支持工業(yè)通信協(xié)議或電機(jī)控制接口的雙核可編程實(shí)時(shí)單元和工業(yè)通信子系統(tǒng) (PRU-ICSS)： \n? PROFINET \n? IO-Link \n? 通用輸入/輸出 (GPIO)\n? 實(shí)時(shí)控制子系統(tǒng) (CONTROLSS)\n? 5 個(gè) 12 位逐次逼近寄存器 (SAR) 模數(shù)轉(zhuǎn)換器 (ADC) \n? 每個(gè) ADC 6 個(gè)可選輸入\n? 帶緩;

TI

德州儀器

AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 頁數(shù)：167 Pages

TI

德州儀器

AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 頁數(shù)：167 Pages

TI

德州儀器

AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 頁數(shù)：167 Pages

TI

德州儀器

AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 頁數(shù)：167 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/am2634c/marking.html">AM2634C；Package：NFBGA；AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 頁數(shù)：167 Pages

TI

德州儀器

絲印：AM2632C；Package：NFBGA；AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 頁數(shù)：167 Pages

TI

德州儀器

AM263x Sitara? Microcontrollers

1 Features Processor Cores: ? Single, dual, and quad-core Arm? Cortex?-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 頁數(shù)：167 Pages

TI

德州儀器