絲印：AE；Package：SOT-353；2-input AND gate

DESCRIPTION The 74AHC1G/AHCT1G08 is a high-speed Si-gate CMOS device. The 74AHC1G/AHCT1G08 provides the 2-input AND function. FEATURES ? Symmetrical output impedance ? High noise immunity ? ESD protection: – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exce

文件：80.09 Kbytes 頁數(shù)：12 Pages

PHI

PHI

絲印：AE；Package：SOT-353；2-input AND gate

DESCRIPTION The 74AHC1G/AHCT1G08 is a high-speed Si-gate CMOS device. The 74AHC1G/AHCT1G08 provides the 2-input AND function. FEATURES ? Symmetrical output impedance ? High noise immunity ? ESD protection: – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exce

文件：75 Kbytes 頁數(shù)：16 Pages

PHI

PHI

絲?。?strong>AE；Package：SOT-353；2-input AND gate

General description 74AHC1G08 and 74AHCT1G08 are high-speed Si-gate CMOS devices. They provide a 2-input AND function. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5

文件：77.68 Kbytes 頁數(shù)：11 Pages

恩XP

絲?。?strong>AE；Package：SOT-353；2-input AND gate

General description 74AHC1G08 and 74AHCT1G08 are high-speed Si-gate CMOS devices. They provide a 2-input AND function. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5

文件：63.22 Kbytes 頁數(shù)：6 Pages

恩XP

絲?。?strong>aE；Package：SOT1089；Low-power dual 2-input NAND Schmitt trigger

1. General description The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IO

文件：309.84 Kbytes 頁數(shù)：21 Pages

NEXPERIA

安世

絲?。?strong>aE；Package：SOT1116；Low-power dual 2-input NAND Schmitt trigger

1. General description The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IO

文件：309.84 Kbytes 頁數(shù)：21 Pages

NEXPERIA

安世

絲印：aE；Package：SOT1203；Low-power dual 2-input NAND Schmitt trigger

1. General description The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IO

文件：309.84 Kbytes 頁數(shù)：21 Pages

NEXPERIA

安世

絲?。?strong>AE；Package：SOT-89；SOT89 PNP SILICON PLANAR MEDIUM POWER TRANSISTORS

SOT89 PNP SILICON PLANAR MEDIUM POWER TRANSISTORS COMPLEMENTARY TYPE – BCX51 – BCX54 BCX52 – BCX55 BCX53 – BCX56

文件：28.4 Kbytes 頁數(shù)：1 Pages

ZETEX

絲印：Ae；Package：SSOP5；Standard CMOS Voltage Detector IC

Description ROHM’s BD48□□G/FVE and BD49□□G/FVE series are highly accurate, low current consumption reset IC series. The lineup was established with tow output types (Nch open drain and CMOS output) and detection voltages range from 2.3V to 6.0V in increments of 0.1V, so that the series may be sel

文件：507.55 Kbytes 頁數(shù)：18 Pages

ROHM

羅姆

絲?。?strong>Ae；Package：SSOP5；Standard CMOS Voltage Detector IC

Description ROHM’s BD48□□G/FVE and BD49□□G/FVE series are highly accurate, low current consumption reset IC series. The lineup was established with tow output types (Nch open drain and CMOS output) and detection voltages range from 2.3V to 6.0V in increments of 0.1V, so that the series may be sel

文件：507.55 Kbytes 頁數(shù)：18 Pages

ROHM

羅姆