12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.26334 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器

12 位、80MSPS 模數(shù)轉(zhuǎn)換器 (ADC)

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve ? Maximum Sample Rate: 125 MSPS\n? 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off\n? Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP\n? Internal Reference with Support for External Reference\n? Programmable Output Clock Position ;

TI

德州儀器

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.26334 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.26334 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.16481 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.42539 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.42539 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.16481 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.26334 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

文件：2.26334 Mbytes 頁(yè)數(shù)：67 Pages

TI

德州儀器