3.1 GHz to 4.2 GHz, Receiver Front End

GENERAL DESCRIPTION The ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. The device operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6 GH

文件：685 Kbytes 頁數(shù)：11 Pages

AD

亞德諾

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ? Integrated RF front end ? LNA and high-power silicon SPDT switch ? On-chip bias and matching ? Single-supply operation ? Gain: 35.5 dB typical at 3.6 GHz ? Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ? Low noise figure: 1.3 dB typical at 3.6 GHz ? Low insertion loss:

文件：686.07 Kbytes 頁數(shù)：11 Pages

AD

亞德諾

3.1 GHz 至 4.2 GHz，接收器前端

ADRF5534 是一款集成 RF 的前端多芯片模塊，設計用于時分雙工 (TDD) 應用。該套件的工作頻率為 3.1 GHz 至 4.2 GHz。ADRF5534 配置有 LNA 和一個大功率硅 SPDT 開關(guān)。\n\n 在 3.6 GHz 的接收過程中，LNA 提供 1.3 dB 的低噪聲指數(shù) (NF) 和 35.5 dB 的高增益，并且具有 ?4 dBm 的三階交調(diào)截點 (IIP3)。\n\n 在發(fā)射過程中，該開關(guān)提供 0.8 dB 的低插入損耗，并在整個生命周期內(nèi)處理 37 dBm 的長期演進 (LTE) 平均功率（8 dB 峰值至平均值比 (PAR)），而在單一事件 ? 集成式 RF 前端\n? LNA 和高功率硅 SPDT 開關(guān)\n? 片內(nèi)偏置和匹配\n? 單電源供電\n? 增益：3.6 GHz 時為 35.5 dB（典型值）\n? 增益平坦度：25°C 下為 1.5 dB（400 MHz 帶寬）\n? 低噪聲指數(shù)：3.6 GHz 時為 1.3 dB（典型值）\n? 低插入損耗：3.6 GHz 時為 0.8 dB（典型值）;

ADI

亞德諾

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ? Integrated RF front end ? LNA and high-power silicon SPDT switch ? On-chip bias and matching ? Single-supply operation ? Gain: 35.5 dB typical at 3.6 GHz ? Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ? Low noise figure: 1.3 dB typical at 3.6 GHz ? Low insertion loss:

文件：686.07 Kbytes 頁數(shù)：11 Pages

AD

亞德諾

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ? Integrated RF front end ? LNA and high-power silicon SPDT switch ? On-chip bias and matching ? Single-supply operation ? Gain: 35.5 dB typical at 3.6 GHz ? Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ? Low noise figure: 1.3 dB typical at 3.6 GHz ? Low insertion loss:

文件：686.07 Kbytes 頁數(shù)：11 Pages

AD

亞德諾

3.1 GHz to 4.2 GHz, Receiver Front End

GENERAL DESCRIPTION The ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. The device operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6 GH

文件：685 Kbytes 頁數(shù)：11 Pages

AD

亞德諾

3.1 GHz to 4.2 GHz, Receiver Front End

GENERAL DESCRIPTION The ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. The device operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6 GH

文件：685 Kbytes 頁數(shù)：11 Pages

AD

亞德諾

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ? Integrated RF front end ? LNA and high-power silicon SPDT switch ? On-chip bias and matching ? Single-supply operation ? Gain: 35.5 dB typical at 3.6 GHz ? Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ? Low noise figure: 1.3 dB typical at 3.6 GHz ? Low insertion loss:

文件：686.07 Kbytes 頁數(shù)：11 Pages

AD

亞德諾

3.1 GHz to 4.2 GHz, Receiver Front End

FEATURES ? Integrated RF front end ? LNA and high-power silicon SPDT switch ? On-chip bias and matching ? Single-supply operation ? Gain: 35.5 dB typical at 3.6 GHz ? Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth ? Low noise figure: 1.3 dB typical at 3.6 GHz ? Low insertion loss:

文件：686.07 Kbytes 頁數(shù)：11 Pages

AD

亞德諾

3.1 GHz to 4.2 GHz, Receiver Front End

GENERAL DESCRIPTION The ADRF5534 is an integrated RF, front-end multichip module designed for time division duplex (TDD) applications. The device operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured with an LNA and a high-power, silicon, SPDT switch. In the receive operation at 3.6 GH

文件：685 Kbytes 頁數(shù)：11 Pages

AD

亞德諾