3.3 V, 100 Mbps, Half- and Full-Duplex

GENERAL DESCRIPTION The ADN4690E/ADN4692E/ADN4694E/ADN4695E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 100 Mbps (50 MHz). Slew rate control is implemented on the driver outputs. The receivers detect the bus state

文件：452.22 Kbytes 頁數(shù)：20 Pages

AD

亞德諾

3.3 V, 200 Mbps, Half- and Full-Duplex

GENERAL DESCRIPTION The ADN4691E/ADN4693E/ADN4696E/ADN4697E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 200 Mbps (100 MHz). The receivers detect the bus state with a differential input of as little as 50 mV over a

文件：364.04 Kbytes 頁數(shù)：20 Pages

AD

亞德諾

LVDS and M-LVDS Circuit Implementation Guide

INTRODUCTION Low voltage differential signaling (LVDS) is a standard for communicating at high speed in point-to-point applications. Multipoint LVDS (M-LVDS) is a similar standard for multipoint applications. Both LVDS and M-LVDS use differential signaling, a two-wire communication method where r

文件：593.25 Kbytes 頁數(shù)：12 Pages

AD

亞德諾

3.3 V, 100 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers

GENERAL DESCRIPTION The ADN4690E/ADN4692E/ADN4694E/ADN4695E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 100 Mbps (50 MHz). Slew rate control is implemented on the driver outputs. The receivers detect the bus state

文件：485.86 Kbytes 頁數(shù)：20 Pages

AD

亞德諾

3.3 V, 200 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers

GENERAL DESCRIPTION The ADN4691E/ADN4693E/ADN4696E/ADN4697E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 200 Mbps (100 MHz). The receivers detect the bus state with a differential input of as little as 50 mV over a

文件：395.64 Kbytes 頁數(shù)：20 Pages

AD

亞德諾

High Speed Evaluation Board for Half-Duplex M-LVDS Transceivers

文件：307.18 Kbytes 頁數(shù)：8 Pages

AD

亞德諾

High Speed Evaluation Board for Full Duplex M-LVDS Transceivers

文件：581.69 Kbytes 頁數(shù)：8 Pages

AD

亞德諾

3.3 V, 100 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers

GENERAL DESCRIPTION The ADN4690E/ADN4692E/ADN4694E/ADN4695E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 100 Mbps (50 MHz). Slew rate control is implemented on the driver outputs. The receivers detect the bus state

文件：485.86 Kbytes 頁數(shù)：20 Pages

AD

亞德諾

3.3 V, 100 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers

GENERAL DESCRIPTION The ADN4690E/ADN4692E/ADN4694E/ADN4695E are multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 100 Mbps (50 MHz). Slew rate control is implemented on the driver outputs. The receivers detect the bus state

文件：485.86 Kbytes 頁數(shù)：20 Pages

AD

亞德諾

帶1型接收機的3.3 V、100 Mbps、全雙工、高速M-LVDS收發(fā)器

ADN4690E/ADN4692E是多點低壓差分信號(M-LVDS)收發(fā)器（驅(qū)動器和接收機對），工作速率最高可達100 Mbps (50 MHz)。驅(qū)動器輸出端實施壓擺率控制，以增強輸出信號完整性，并較大程度地減少反射。接收機可在-1 V至+3.4 V的共模電壓范圍內(nèi)利用低至50 mV的差分輸入檢測總線狀態(tài)?？偩€引腳上提供最高可達±15 kV的ESD保護。 ADN4690E/ADN4692E遵循M-LVDS的TIA/EIA-899標準，為TIA/EIA-644 LVDS器件添加了額外的多點能力。該驅(qū)動器在多點總線拓撲結(jié)構(gòu)上允許低至30 Ω的總線負載，且控制驅(qū)動器輸出轉(zhuǎn)換時間以較大程度 ? 多點LVDS收發(fā)器（低電壓差分信號驅(qū)動器和接收器對）\n\n? 開關速率： 100 Mbps (50 MHz)\n\n? 支持的總線負載： 30 ?至55 ?\n\n? 2類接收器可供選擇\n? 1類(ADN4690E/ADN4692E)： 遲滯為25 mV;

ADI

亞德諾