3 V LVDS Quad CMOS Differential Line Receiver

GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow through pin configuration for easy PCB layout and separation of input and output sign

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3 V LVDS Quad CMOS Differential Line Receiver

GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow through pin configuration for easy PCB layout and separation of input and output sign

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LVDS and M-LVDS Circuit Implementation Guide

INTRODUCTION Low voltage differential signaling (LVDS) is a standard for communicating at high speed in point-to-point applications. Multipoint LVDS (M-LVDS) is a similar standard for multipoint applications. Both LVDS and M-LVDS use differential signaling, a two-wire communication method where r

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3 V LVDS Quad CMOS Differential Line Receiver

GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pin configuration for easy PCB layout and separation of input and output signal

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3 V LVDS 四通道CMOS差分線接收器

ADN4668是一款四通道CMOS低壓差分信號(hào)（LVDS）線接收器，提供400 Mbps（200 MHz）以上的數(shù)據(jù)速率及超低功耗。ADN4668具有流通引腳配置，可以輕松實(shí)現(xiàn)印制電路板布線以及輸入信號(hào)與輸出信號(hào)的分離。這款器件接收低壓（典型值310 mV）差分輸入信號(hào)，并將其轉(zhuǎn)換為單端3 V TTL/CMOS邏輯電平。\n\n ADN4668還提供高電平有效和低電平有效的啟用/禁用輸入（EN 和/EN），以控制全部的4個(gè)接收器。它們可禁用接收器，并將輸出切換為高阻抗?fàn)顟B(tài)。這個(gè)高阻抗?fàn)顟B(tài)允許對(duì)一個(gè)或多個(gè)ADN4668的輸出進(jìn)行多路復(fù)用，以將待機(jī)功耗降低至3 mW（典型值）。ADN46 ? 接收器輸入引腳提供±15 kV ESD保護(hù)\n\n? 開關(guān)速率：400 Mbps（200 MHz）\n\n? 流通引腳配置簡(jiǎn)化印制電路板布線 \n\n? 通道到通道偏移：150 ps（典型值） \n\n? 差分偏移：100 ps（典型值） \n\n? 傳播延遲：2.7 ns（最大值）\n\n\n\n? 電源電壓：3.3 V\n\n? 斷電時(shí)具有高阻抗輸出\n\n? 低功耗設(shè)計(jì)（待機(jī)功耗典型值為3 mW）\n\n? 可與現(xiàn)有的5 V LVDS驅(qū)動(dòng)器配合使用\n\n? 接收小擺幅（典型值310 mV ）差分輸入信號(hào)電平\n\n? 支持開路、短路，以及終止輸入故障安全;

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3 V LVDS Quad CMOS Differential Line Receiver

GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pin configuration for easy PCB layout and separation of input and output signal

文件：286.98 Kbytes 頁(yè)數(shù)：12 Pages

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3 V LVDS Quad CMOS Differential Line Receiver

GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pin configuration for easy PCB layout and separation of input and output signal

文件：286.98 Kbytes 頁(yè)數(shù)：12 Pages

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3 V LVDS Quad CMOS Differential Line Receiver

GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow through pin configuration for easy PCB layout and separation of input and output sign

文件：306.93 Kbytes 頁(yè)數(shù)：12 Pages

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3 V LVDS Quad CMOS Differential Line Receiver

GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow through pin configuration for easy PCB layout and separation of input and output sign

文件：286.98 Kbytes 頁(yè)數(shù)：12 Pages

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3 V LVDS Quad CMOS Differential Line Receiver

GENERAL DESCRIPTION The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow through pin configuration for easy PCB layout and separation of input and output sign

文件：306.93 Kbytes 頁(yè)數(shù)：12 Pages

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