Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

FEATURES Serial data input: 8.5 Gbps to 11.3 Gbps No reference clock required Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 9.2 mV p-p typical (limiting amplifier mode) Optional limiting amplifier and equalizer inputs Programmable jitter transfer b

文件：509.87 Kbytes 頁數(shù)：32 Pages

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Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

文件：703.27 Kbytes 頁數(shù)：32 Pages

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連續(xù)速率8.5 Gbps 至11.3 Gbps 時鐘和數(shù)據(jù)恢復(fù)IC，集成限幅放大器/均衡器

ADN2917可提供下列接收器功能：量化、信號電平檢測、時鐘和數(shù)據(jù)恢復(fù)，適用于從8.5 Gbps到11.3 Gbps的連續(xù)數(shù)據(jù)速率。它可自動鎖定至所有數(shù)據(jù)速率，而無需外部參考時鐘或編程。ADN2917抖動性能超越全部SONET/SDH抖動要求，包括抖動傳遞、抖動產(chǎn)生和抖動容差。\n\n ADN2917提供手動或自動限幅調(diào)整和手動采樣相位調(diào)整。此外，用戶還可選擇在輸入端連接一個限幅放大器或均衡器。均衡器為自適應(yīng)或可手動設(shè)置。\n\n 當(dāng)輸入信號電平降至用戶可編程閾值以下時，接收器前端信號丟失(LOS)檢測電路會予以提示。LOS檢測電路具有遲滯特性，可防止LOS輸出震顫。此外， ? 串行數(shù)據(jù)輸入：8.5 Gbps至11.3 Gbps\n\n? 無需參考時鐘\n\n? 超過SONET/SDH抖動傳遞/產(chǎn)生/容差要求\n\n? 量化器靈敏度：9.2 mV p-p（典型值，限幅放大器模式）\n\n? 可選限幅放大器和均衡器輸入\n\n? 可編程抖動傳遞帶寬，支持G.8251 OTN\n\n? 可編程限幅電平\n\n? 采樣相位調(diào)整\n\n? 輸出極性反轉(zhuǎn)\n\n? 通過I2C可編程LOS閾值\n\n? 通過I2C訪問可選特性\n\n? LOS報警（僅限幅放大器模式）\n\n? LOL指示器\n\n? PRBS發(fā)生器/檢測器\n\n? 應(yīng)用敏感的功耗調(diào)整\n? 352 mW（;

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Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

FEATURES Serial data input: 8.5 Gbps to 11.3 Gbps No reference clock required Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 9.2 mV p-p typical (limiting amplifier mode) Optional limiting amplifier and equalizer inputs Programmable jitter transfer b

文件：509.87 Kbytes 頁數(shù)：32 Pages

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Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

FEATURES Serial data input: 8.5 Gbps to 11.3 Gbps No reference clock required Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 9.2 mV p-p typical (limiting amplifier mode) Optional limiting amplifier and equalizer inputs Programmable jitter transfer b

文件：509.87 Kbytes 頁數(shù)：32 Pages

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Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

FEATURES Serial data input: 8.5 Gbps to 11.3 Gbps No reference clock required Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 9.2 mV p-p typical (limiting amplifier mode) Optional limiting amplifier and equalizer inputs Programmable jitter transfer b

文件：509.87 Kbytes 頁數(shù)：32 Pages

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Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

文件：703.27 Kbytes 頁數(shù)：32 Pages

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Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

文件：703.27 Kbytes 頁數(shù)：32 Pages

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Package：24-WFQFN 裸露焊盤，CSP；包裝：托盤 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC CLK/DATA REC 11.3 GBPS 24LFCS

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Package：24-WFQFN 裸露焊盤，CSP；包裝：托盤 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC CLK/DATA REC 11.3 GBPS 24LFCS

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