Low Phase Noise, Fast Settling PLL Frequency Synthesizer

GENERAL DESCRIPTION The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It cons

文件：590.92 Kbytes 頁數(shù)：28 Pages

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低相位噪聲、快速建立PLL頻率合成器

ADF4193頻率合成器可以用來在無線接收機和發(fā)射機的上變頻和下變頻部分實現(xiàn)本振，其結(jié)構(gòu)經(jīng)過特別設(shè)計，符合基站的GSM/EDGE鎖定時間要求。它由低噪聲數(shù)字鑒頻鑒相器(PFD)和精密差分電荷泵組成。還有一個差分放大器，用來將電荷泵的差分輸出轉(zhuǎn)換為外部電壓控制振蕩器(VCO)的單端電壓。\n\n Σ-Δ型小數(shù)插值器與N分頻器一起使用，能夠?qū)崿F(xiàn)可編程模數(shù)小數(shù)N分頻。此外，4位參考(R)分頻器和片內(nèi)倍頻器允許PFD輸入端的參考信號(REFIN)頻率為可選值。如果頻率合成器與外部環(huán)路濾波器和VCO一起使用，則可以實現(xiàn)完整的鎖相環(huán)(PLL)。開關(guān)結(jié)構(gòu)確保PLL能在GSM時隙保護期間內(nèi)建立，而無 ? 新型快速建立小數(shù)N分頻PLL結(jié)構(gòu)\n? 單個PLL可取代乒乓式頻率合成器\n? 在5 μs內(nèi)完成整個GSM頻段上的跳頻，相位建立時間為20 μs\n? 相位誤差：0.5°均方根值（2 GHz RF輸出）\n? 數(shù)字可編程輸出相位;

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Low Phase Noise, Fast Settling PLL Frequency Synthesizer

GENERAL DESCRIPTION The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It cons

文件：590.92 Kbytes 頁數(shù)：28 Pages

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Low Phase Noise, Fast Settling PLL Frequency Synthesizer

GENERAL DESCRIPTION The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It cons

文件：590.92 Kbytes 頁數(shù)：28 Pages

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Low Phase Noise, Fast Settling PLL Frequency Synthesizer

GENERAL DESCRIPTION The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It cons

文件：590.92 Kbytes 頁數(shù)：28 Pages

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Low Phase Noise, Fast Settling PLL Frequency Synthesizer

文件：922.08 Kbytes 頁數(shù)：32 Pages

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Package：32-WFQFN 裸露焊盤，CSP；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL FREQ SYNTHESIZER 32LFCSP

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Package：32-WFQFN 裸露焊盤，CSP；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL FREQ SYNTHESIZER 32LFCSP

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Package：32-WFQFN 裸露焊盤，CSP；包裝：托盤 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC PLL FREQ SYNTHESIZER 32LFCSP

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