200 MHz Clock Generator PLL

GENERAL DESCRIPTION The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable

文件：190.66 Kbytes 頁數(shù)：16 Pages

AD

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200 MHz 時鐘發(fā)生器PLL

ADF4001頻率合成器可用來實現(xiàn)要求極低噪聲、穩(wěn)定基準信號的PLL的時鐘源。它由低噪聲數(shù)字鑒頻鑒相器(PFD)、精密電荷泵、可編程參考分頻器和可編程13位N分頻器組成。此外，14位參考分頻器（R分頻器）允許PFD輸入端的REFIN頻率為可選值。如果頻率合成器與外部環(huán)路濾波器和電壓控制振蕩器(VCO)或電壓控制晶體振蕩器(VCXO)一起使用，則可以實現(xiàn)完整的鎖相環(huán)(PLL)。N的最小值為1，這為時鐘產(chǎn)生提供了靈活性。 ? 200 MHz帶寬\n\n? 電源電壓范圍：2.7 V至5.5 V\n\n? 可編程電荷泵電流;

ADI

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50 MHz to 1000 MHz Quadrature Demodulator

GENERAL DESCRIPTION The AD8348 is a broadband quadrature demodulator with an integrated intermediate frequency (IF), variable gain amplifier (VGA), and integrated baseband amplifiers. It is suitable for use in communications receivers, performing quadrature demodulation from IF directly to baseba

文件：929.43 Kbytes 頁數(shù)：28 Pages

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200 MHz Clock Generator PLL

GENERAL DESCRIPTION The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable

文件：190.66 Kbytes 頁數(shù)：16 Pages

AD

亞德諾

200 MHz Clock Generator PLL

GENERAL DESCRIPTION The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable

文件：190.66 Kbytes 頁數(shù)：16 Pages

AD

亞德諾

50 MHz to 1000 MHz Quadrature Demodulator

GENERAL DESCRIPTION The AD8348 is a broadband quadrature demodulator with an integrated intermediate frequency (IF), variable gain amplifier (VGA), and integrated baseband amplifiers. It is suitable for use in communications receivers, performing quadrature demodulation from IF directly to baseba

文件：929.43 Kbytes 頁數(shù)：28 Pages

AD

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200 MHz Clock Generator PLL

文件：860.61 Kbytes 頁數(shù)：17 Pages

AD

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200 MHz Clock Generator PLL

文件：860.61 Kbytes 頁數(shù)：17 Pages

AD

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200 MHz Clock Generator PLL

文件：860.61 Kbytes 頁數(shù)：17 Pages

AD

亞德諾

200 MHz Clock Generator PLL

文件：860.61 Kbytes 頁數(shù)：17 Pages

AD

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