ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features ? Dual channel ADC ? 18-bit 10, 25, 65 MSPS ADC ? Noise floor: -160 dBFS/Hz ? Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) ? Latency: 1-2 clock cycles ? 18-bit, no missing codes ? INL/DNL: ±7/ ±0.7 LSB (typical) ? Reference: external or intern

文件：5.67705 Mbytes 頁數(shù)：85 Pages

TI

德州儀器

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features ? Dual channel ADC ? 18-bit 10, 25, 65 MSPS ADC ? Noise floor: -160 dBFS/Hz ? Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) ? Latency: 1-2 clock cycles ? 18-bit, no missing codes ? INL/DNL: ±7/ ±0.7 LSB (typical) ? Reference: external or intern

文件：5.98943 Mbytes 頁數(shù)：91 Pages

TI

德州儀器

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

文件：4.43597 Mbytes 頁數(shù)：73 Pages

TI

德州儀器

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

文件：5.03782 Mbytes 頁數(shù)：75 Pages

TI

德州儀器

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

文件：5.01183 Mbytes 頁數(shù)：75 Pages

TI

德州儀器

Dual-channel, 18-bit, 25-MSPS, low-noise, ultra-low-power analog-to-digital converter (ADC)

ADC3681、ADC3682、ADC3683 (ADC368x) 屬于低噪聲、超低功耗、18 位、65MSPS 高速雙通道 ADC 系列器件。該器件可實(shí)現(xiàn)超低噪聲性能和 -160dBFS/Hz 的噪聲頻譜密度，還具有出色的線性度和動(dòng)態(tài)范圍。ADC368x 可提供出色的直流精度以及中頻采樣支持，因此非常適合各種應(yīng)用。高速控制環(huán)路受益于低至僅一個(gè)時(shí)鐘周期的低延遲。該 ADC 在 65Msps 下的功耗僅為每通道 94mW，且其功耗隨采樣率減小而迅速降低。\n\nADC368x 使用串行 LVDS (SLVDS) 接口輸出數(shù)據(jù)，可更大限度減少數(shù)字互連的次數(shù)。該器件提供雙通道、單通道和半通道選項(xiàng)。A ? 雙通道 ADC\n? 本底噪聲：-160dBFS/Hz\n? 延遲：1-2 個(gè)時(shí)鐘周期\n? INL/DNL：±7/±0.7LSB（典型值）\n? 輸入帶寬：900MHz (3dB)\n? 片上數(shù)字濾波器（可選） \n? 32 位 NCO\n? 串行 LVDS 數(shù)字接口（2 線、1 線和 1/2 線）\n? 頻譜性能 (fIN = 5MHz)： \n? SFDR：89dBc HD2、HD3\n? 頻譜性能 (fIN = 20MHz)： \n? SFDR：85dBc HD2、HD3\n? SFDR：97dBFS 最嚴(yán)重毛刺;

TI

德州儀器

絲印：AZ3682；Package：WQFN；ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features ? Dual channel ADC ? 18-bit 10, 25, 65 MSPS ADC ? Noise floor: -160 dBFS/Hz ? Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) ? Latency: 1-2 clock cycles ? 18-bit, no missing codes ? INL/DNL: ±7/ ±0.7 LSB (typical) ? Reference: external or intern

文件：5.67705 Mbytes 頁數(shù)：85 Pages

TI

德州儀器

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features ? Dual channel ADC ? 18-bit 10, 25, 65 MSPS ADC ? Noise floor: -160 dBFS/Hz ? Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) ? Latency: 1-2 clock cycles ? 18-bit, no missing codes ? INL/DNL: ±7/ ±0.7 LSB (typical) ? Reference: external or intern

文件：5.98943 Mbytes 頁數(shù)：91 Pages

TI

德州儀器

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features ? Dual channel ADC ? 18-bit 10, 25, 65 MSPS ADC ? Noise floor: -160 dBFS/Hz ? Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) ? Latency: 1-2 clock cycles ? 18-bit, no missing codes ? INL/DNL: ±7/ ±0.7 LSB (typical) ? Reference: external or intern

文件：5.98943 Mbytes 頁數(shù)：91 Pages

TI

德州儀器

ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC

1 Features ? Dual channel ADC ? 18-bit 10, 25, 65 MSPS ADC ? Noise floor: -160 dBFS/Hz ? Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS) ? Latency: 1-2 clock cycles ? 18-bit, no missing codes ? INL/DNL: ±7/ ±0.7 LSB (typical) ? Reference: external or intern

文件：5.98943 Mbytes 頁數(shù)：91 Pages

TI

德州儀器