Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V

GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynami

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Analog-to-Digital Converter

文件：1.22964 Mbytes 頁數(shù)：42 Pages

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4通道、16位、125 MSPS串行LVDS 1.8 V模數(shù)轉(zhuǎn)換器

AD9653是一款4通道、16位、125 MSPS模數(shù)轉(zhuǎn)換器(ADC)，內(nèi)置片內(nèi)采樣保持電路，專門針對低成本、低功耗、小尺寸和易用性而設(shè)計。該產(chǎn)品的轉(zhuǎn)換速率最高可達125 MSPS，具有杰出的動態(tài)性能與低功耗特性，對小封裝尺寸的應(yīng)用很有意義。\n\n 該ADC要求采用1.8 V單電源供電以及LVPECL/CMOS/LVDS兼容型采樣速率時鐘信號，以便充分發(fā)揮其工作性能。對于大多數(shù)應(yīng)用來說，無需外部基準電壓源或驅(qū)動器件。\n\n 為獲得合適的LVDS串行數(shù)據(jù)速率，該ADC會自動倍乘采樣速率時鐘。它提供一個數(shù)據(jù)時鐘輸出(DCO)用于在輸出端捕獲數(shù)據(jù)，以及一個幀時鐘輸出(FCO) ? 1.8 V電源供電 \n\n? 低功耗：每通道164 mW（125 MSPS），功率選項可調(diào)整 \n\n? 信噪比(SNR)：76.5 dBFS（70 MHz，2.0Vp-p輸入范圍） \n\n? 信噪比(SNR)：77.5 dBFS（70 MHz，2.6Vp-p輸入范圍） \n\n? 無雜散動態(tài)范圍(SFDR)：90 dBc（至Nyquist頻率）\n\n? DNL = ±0.7 LSB（典型值）；INL = ±3.5 LSB（典型值） \n\n? 串行LVDS（ANSI-644，默認）、低功耗，減少信號選項（類似于IEEE 1596.3） \n\n? 650 MHz全功率模擬帶寬 \n;

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Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V

GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynami

文件：1.2382 Mbytes 頁數(shù)：40 Pages

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Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V

GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynami

文件：1.2382 Mbytes 頁數(shù)：40 Pages

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Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V

GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynami

文件：1.2382 Mbytes 頁數(shù)：40 Pages

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Analog-to-Digital Converter

文件：1.22964 Mbytes 頁數(shù)：42 Pages

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Analog-to-Digital Converter

文件：1.22964 Mbytes 頁數(shù)：42 Pages

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Analog-to-Digital Converter

文件：1.22964 Mbytes 頁數(shù)：42 Pages

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Analog-to-Digital Converter

文件：1.22964 Mbytes 頁數(shù)：42 Pages

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