16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

GENERAL DESCRIPTION The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz. The dual ADC core features a multistage, differential pipelined archit

文件：1.6669 Mbytes 頁數(shù)：44 Pages

AD

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16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

GENERAL DESCRIPTION The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz. The dual ADC core features a multistage, differential pipelined archit

文件：1.6669 Mbytes 頁數(shù)：44 Pages

AD

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16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

GENERAL DESCRIPTION The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz. The dual ADC core features a multistage, differential pipelined archit

文件：1.6669 Mbytes 頁數(shù)：44 Pages

AD

亞德諾

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

GENERAL DESCRIPTION The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz. The dual ADC core features a multistage, differential pipelined archit

文件：1.6669 Mbytes 頁數(shù)：44 Pages

AD

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Dual 16-Bit, 105 MSPS, 1.8 V Analog-to-Digital Converter

文件：252.97 Kbytes 頁數(shù)：12 Pages

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Dual 16-Bit, 105 MSPS, 1.8 V Analog-to-Digital Converter

文件：252.97 Kbytes 頁數(shù)：12 Pages

AD

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Dual 16-Bit, 105 MSPS, 1.8 V Analog-to-Digital Converter

文件：252.97 Kbytes 頁數(shù)：12 Pages

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16位、25 MSPS/65 MSPS/80 MSPS/105 MSPS模數(shù)轉(zhuǎn)換器

AD9650是一款雙通道、16位、25 MSPS/65 MSPS/80 MSPS/ 105 MSPS模數(shù)轉(zhuǎn)換器(ADC)，專為數(shù)字化高頻、寬動態(tài)范圍信號而設(shè)計(jì)，支持輸入頻率高達(dá)300 MHz。\n這款雙通道ADC內(nèi)核采用多級、差分流水線架構(gòu)，并集成了輸出糾錯邏輯。每個ADC均具有寬帶寬、差分采樣保持模擬輸入放大器和共享集成基準(zhǔn)電壓源，可簡化設(shè)計(jì)考慮因素。占空比穩(wěn)定器可用來補(bǔ)償ADC時鐘占空比的波動，使轉(zhuǎn)換器保持出色的性能。\nADC輸出數(shù)據(jù)可以直接送至兩個外部16位輸出端口，或在單個16位總線上多路復(fù)用。這些輸出可以設(shè)置為1.8 V CMOS或LVDS。\n需要時，靈活的掉電選項(xiàng)可以明顯降低功 1.8 V 模擬電源供電\n1.8 V CMOS或LVDS輸出電源\nSNR\n82 dBFS（30 MHz輸入、105 MSPS數(shù)據(jù)速率）\n83 dBFS（9.7 MHz輸入、25 MSPS數(shù)據(jù)速率）\nSFDR\n90 dBc（30 MHz輸入、105 MSPS數(shù)據(jù)速率）\n95 dBc（9.7 MHz輸入、25 MSPS數(shù)據(jù)速率）\n低功耗：\n每個通道328 mW (105 MSPS)\n每個通道119 mW (25 MSPS)\n1至8整數(shù)輸入時鐘分頻器\n中頻采樣頻率達(dá)300 MHz\n模擬輸入范圍：2.7 V p-p\n可選片內(nèi)擾動\n集成ADC采樣保持輸入\n差分模擬輸入、5;

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包裝：盒 類別：開發(fā)板，套件，編程器 評估板 - 模數(shù)轉(zhuǎn)換器（ADC） 描述：BOARD EVAL FOR AD9650

AD

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Package：64-VFQFN 裸露焊盤，CSP；包裝：管件 類別：集成電路（IC） 模數(shù)轉(zhuǎn)換器（ADC） 描述：IC ADC 16BIT PIPELINED 64LFCSP

AD

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