Quad, 12-Bit, 80 MSPS/105 MSPS

GENERAL DESCRIPTION The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-andhold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outs

文件：1.91662 Mbytes 頁數(shù)：40 Pages

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125 MSPS, Serial LVDS 1.8 V ADC

文件：1.20888 Mbytes 頁數(shù)：42 Pages

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四通道、12位、80/105/125 MSPS、串行LVDS 1.8V ADC

AD9633是一款四通道、12位、80 MSPS/105 MSPS/125 MSPS 模數(shù)轉(zhuǎn)換器（ADC），具有片內(nèi)采樣保持電路，旨在實現(xiàn)低成本、低功耗、小尺寸和易用性。該產(chǎn)品以高達 125 MSPS 的轉(zhuǎn)換速率運行，并針對要求小封裝尺寸至關(guān)重要的應(yīng)用進行了優(yōu)化，以實現(xiàn)出色的動態(tài)性能和低功耗。\n\n 該 ADC 需要單個 1.8 V 電源和兼容 LVPECL//CMOS/LVDS 的采樣率時鐘，以實現(xiàn)全性能運行。在許多應(yīng)用中，不需要外部參考或驅(qū)動程序組件。\n\n ADC 自動將采樣率時鐘乘以合適的 LVDS 串行數(shù)據(jù)速率。提供了用于在輸出上捕獲數(shù)據(jù)的數(shù)據(jù)時鐘輸出（DCO ? 1.8 V 電源操作\n\n? 低功耗：125 MSPS 時每通道 100 mW，具有可擴展的電源選項\n\n? SNR = 71 dB（至奈奎斯特（Nyquist））\n\n? SFDR = 91 dBc（至奈奎斯特（Nyquist））\n\n? DNL = ±0.3 LSB (典型值); INL = ±0.5 LSB (典型值)\n\n? 串行 LVDS（默認為 ANSI-644）和低功耗、降低信號選項（類似于 IEEE 1596.3）\n\n? 650 MHz 全功率模擬帶寬\n\n? 2 V P-P 輸入電壓范圍;

ADI

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Quad, 12-Bit, 80 MSPS/105 MSPS

GENERAL DESCRIPTION The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-andhold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outs

文件：1.91662 Mbytes 頁數(shù)：40 Pages

AD

亞德諾

Quad, 12-Bit, 80 MSPS/105 MSPS

GENERAL DESCRIPTION The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-andhold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outs

文件：1.91662 Mbytes 頁數(shù)：40 Pages

AD

亞德諾

Quad, 12-Bit, 80 MSPS/105 MSPS

GENERAL DESCRIPTION The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-andhold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outs

文件：1.91662 Mbytes 頁數(shù)：40 Pages

AD

亞德諾

Quad, 12-Bit, 80 MSPS/105 MSPS

GENERAL DESCRIPTION The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-andhold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outs

文件：1.91662 Mbytes 頁數(shù)：40 Pages

AD

亞德諾

Quad, 12-Bit, 80 MSPS/105 MSPS

GENERAL DESCRIPTION The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-andhold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outs

文件：1.91662 Mbytes 頁數(shù)：40 Pages

AD

亞德諾

Quad, 12-Bit, 80 MSPS/105 MSPS

GENERAL DESCRIPTION The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-andhold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outs

文件：1.91662 Mbytes 頁數(shù)：40 Pages

AD

亞德諾

Quad, 12-Bit, 80 MSPS/105 MSPS

GENERAL DESCRIPTION The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-andhold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outs

文件：1.91662 Mbytes 頁數(shù)：40 Pages

AD

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