10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ? SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ? SFDR = 81 dBc to 70 MHz at 150 MSPS ? Low power: 825 mW at 150 MSPS ? 1.8 V analog supply operation ? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ? Integer 1 to 8 input clock divider ? Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 頁(yè)數(shù)：72 Pages

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1.8 V Dual Analog-to-Digital Converter

文件：2.33584 Mbytes 頁(yè)數(shù)：73 Pages

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10位、105 MSPS/125 MSPS/150 MSPS、1.8 V雙核模數(shù)轉(zhuǎn)換器

AD9600是一款雙核、10位、105 MSPS/125 MSPS/150 MSPS ADC，旨在支持要求低成本、小尺寸和多功能特性的通信應(yīng)用。 這款雙核ADC采用多級(jí)、差分流水線架構(gòu)，并集成了輸出糾錯(cuò)邏輯。每個(gè)ADC均具有寬帶寬、差分采樣保持模擬輸入放大器，支持用戶可選的各種輸入范圍。集成基準(zhǔn)電壓源可簡(jiǎn)化設(shè)計(jì)。占空比穩(wěn)定器可用來(lái)補(bǔ)償ADC時(shí)鐘占空比的波動(dòng)，使轉(zhuǎn)換器保持出色的性能。\n\n AD9600內(nèi)置多種功能，可以簡(jiǎn)化通信接收機(jī)中的自動(dòng)增益控制（AGC）功能。例如，快速檢測(cè)特性可以通過(guò)輸出四位輸入電平信息實(shí)現(xiàn)快速檢測(cè)超量程輸入，并且延遲極短。此外，利用ADC的4個(gè)快速 ? 信噪比（SNR）：60.6 dBc\n（61.6 dBFS，至70 MHz、150 MSPS）\n\n? 無(wú)雜散動(dòng)態(tài)范圍（SFDR）：\n81 dBc（至70 MHz、150 MSPS）\n\n? 低功耗：825 mW（150 MSPS）\n\n? 1.8 V模擬電源供電\n\n? 1.8 V至3.3 V CMOS輸出電源或1.8 V LVDS電源\n\n? 1至8整數(shù)輸入時(shí)鐘除法器;

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10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ? SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ? SFDR = 81 dBc to 70 MHz at 150 MSPS ? Low power: 825 mW at 150 MSPS ? 1.8 V analog supply operation ? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ? Integer 1 to 8 input clock divider ? Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 頁(yè)數(shù)：72 Pages

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10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ? SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ? SFDR = 81 dBc to 70 MHz at 150 MSPS ? Low power: 825 mW at 150 MSPS ? 1.8 V analog supply operation ? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ? Integer 1 to 8 input clock divider ? Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 頁(yè)數(shù)：72 Pages

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10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ? SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ? SFDR = 81 dBc to 70 MHz at 150 MSPS ? Low power: 825 mW at 150 MSPS ? 1.8 V analog supply operation ? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ? Integer 1 to 8 input clock divider ? Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 頁(yè)數(shù)：72 Pages

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10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ? SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ? SFDR = 81 dBc to 70 MHz at 150 MSPS ? Low power: 825 mW at 150 MSPS ? 1.8 V analog supply operation ? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ? Integer 1 to 8 input clock divider ? Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 頁(yè)數(shù)：72 Pages

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10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ? SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ? SFDR = 81 dBc to 70 MHz at 150 MSPS ? Low power: 825 mW at 150 MSPS ? 1.8 V analog supply operation ? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ? Integer 1 to 8 input clock divider ? Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 頁(yè)數(shù)：72 Pages

AD

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10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ? SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ? SFDR = 81 dBc to 70 MHz at 150 MSPS ? Low power: 825 mW at 150 MSPS ? 1.8 V analog supply operation ? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ? Integer 1 to 8 input clock divider ? Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 頁(yè)數(shù)：72 Pages

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亞德諾

10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ? SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ? SFDR = 81 dBc to 70 MHz at 150 MSPS ? Low power: 825 mW at 150 MSPS ? 1.8 V analog supply operation ? 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ? Integer 1 to 8 input clock divider ? Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 頁(yè)數(shù)：72 Pages

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