Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 頁數(shù)：20 Pages

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整數(shù)N分頻時鐘轉(zhuǎn)換器，適合有線通信應(yīng)用

AD9550是一款基于鎖相環(huán)(PLL)的時鐘轉(zhuǎn)換器，針對有線通信和基站應(yīng)用的需求而設(shè)計。它采用整數(shù)N分頻PLL來滿足相關(guān)的頻率轉(zhuǎn)換要求。REF輸入端支持單端輸入?yún)⒖夹盘?。\n\n AD9550的引腳可編程，提供從15個可能的輸入頻率轉(zhuǎn)換到51個可能的輸出頻率對（OUT1和OUT2）的標準輸入/輸出頻率轉(zhuǎn)換矩陣。\n\n 雖然AD9550嚴格按照CMOS工藝制造，但其輸出與LVPECL、LVDS或單端CMOS邏輯電平兼容。\n\n AD9550的工作溫度范圍為?40°C至+85°C工業(yè)溫度范圍。 ? 將預(yù)設(shè)標準輸入頻率轉(zhuǎn)換為標準輸出頻率 \n? 輸入頻率范圍：8 kHz至200 MHz \n? 輸出頻率最高可達810 MHz LVPECL和LVDS (200 MHz CMOS) \n? 預(yù)設(shè)引腳可編程頻率轉(zhuǎn)換比 \n? 片內(nèi)VCO;

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Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 頁數(shù)：20 Pages

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亞德諾

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 頁數(shù)：20 Pages

AD

亞德諾

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 頁數(shù)：20 Pages

AD

亞德諾

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

文件：406.17 Kbytes 頁數(shù)：20 Pages

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包裝：盒 功能：時鐘緩沖器/驅(qū)動器/接收器/轉(zhuǎn)換器 類別：開發(fā)板，套件，編程器 評估和演示板及套件 描述：BOARD EVALUATION FOR AD9550

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Package：32-WFQFN 裸露焊盤，CSP；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC INTEGER-N TRANSLATOR 32-LFCSP

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Package：32-WFQFN 裸露焊盤，CSP；包裝：卷帶（TR）剪切帶（CT）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC INTEGER-N TRANSLATOR 32-LFCSP

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