655 MHz Low Jitter Clock Generator

PRODUCT OVERVIEW The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phase-locked loop) circuitry, including a flexible 2

文件：485.42 Kbytes 頁數(shù)：32 Pages

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655 MHz Low Jitter Clock Generator

文件：588.82 Kbytes 頁數(shù)：32 Pages

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低抖動、基于DDS的時鐘發(fā)生器和頻率合成器

AD9540支持多種功能，包括信號合成和低抖動時鐘發(fā)生，適合各種應(yīng)用。該器件內(nèi)置高性能PLL電路，包括靈活的200 MHz鑒頻鑒相器和數(shù)字控制電荷泵電流。它還可以使低抖動、655 MHz CML模式（PECL兼容）輸出驅(qū)動器具有可編程壓擺率。器件支持最高2.7 GHz的外部VCO速率。片上400 MSPS DDS提供及精密的調(diào)諧分辨率和相位編程能力。信息通過一個串行I/O端口載入AD9540中，該端口的器件寫入速度為25Mb/s。還可以對AD9540分頻器模塊進(jìn)行編程，支持?jǐn)U頻時鐘模式。\n\n AD9540的額定工作溫度范圍為-40℃至+85℃擴展汽車應(yīng)用溫度范圍。 ? 出色的內(nèi)在抖動性能\n\n? 200 MHz鑒頻鑒相器輸入\n\n? 655 MHz可編程輸入分頻器用于鑒頻鑒相器(÷M,N) {M,N =1..16}（可旁路）\n\n? 可編程RF分頻器(÷R) {R = 1、2、4、8}（可旁路）\n\n? 8個可編程相位/頻率配置文件\n\n? 400 MSPS內(nèi)部DDS時鐘速度\n\n? 48位頻率調(diào)諧字分辨率;

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655 MHz Low Jitter Clock Generator

PRODUCT OVERVIEW The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phase-locked loop) circuitry, including a flexible 2

文件：485.42 Kbytes 頁數(shù)：32 Pages

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亞德諾

655 MHz Low Jitter Clock Generator

PRODUCT OVERVIEW The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phase-locked loop) circuitry, including a flexible 2

文件：485.42 Kbytes 頁數(shù)：32 Pages

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亞德諾

655 MHz Low Jitter Clock Generator

PRODUCT OVERVIEW The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phase-locked loop) circuitry, including a flexible 2

文件：485.42 Kbytes 頁數(shù)：32 Pages

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655 MHz Low Jitter Clock Generator

文件：846.91 Kbytes 頁數(shù)：32 Pages

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655 MHz Low Jitter Clock Generator

文件：588.82 Kbytes 頁數(shù)：32 Pages

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655 MHz Low Jitter Clock Generator

文件：588.82 Kbytes 頁數(shù)：32 Pages

AD

亞德諾

655 MHz Low Jitter Clock Generator

文件：588.82 Kbytes 頁數(shù)：32 Pages

AD

亞德諾