Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 頁數(shù)：48 Pages

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AD9525旨在滿足長(zhǎng)期演進(jìn)(LTE)和多載波GSM基站設(shè)計(jì)的轉(zhuǎn)換器時(shí)鐘要求。

AD9525旨在滿足長(zhǎng)期演進(jìn)(LTE)和多載波GSM基站設(shè)計(jì)的轉(zhuǎn)換器時(shí)鐘要求。\n\n AD9525提供低功耗、多路輸出時(shí)鐘分配功能，具有低抖動(dòng)性能，并且片內(nèi)集成鎖相環(huán)（PLL），可以配合外部VCO或VCXO使用。VCO輸入和八個(gè)LVPECL輸出最高工作頻率為3.6 GHz。所有輸出共用一個(gè)分頻器，分頻范圍為1到6。\n\n AD9525提供了一個(gè)專用輸出，可用于提供一個(gè)用于重置或同步數(shù)據(jù)轉(zhuǎn)換器的可編程信號(hào)。輸出信號(hào)可以通過一個(gè)SPI寫入操作激活。\n\n AD9525提供48引腳LFCSP封裝，可以采用3.3 V單電源供電。外部VCXO或VCO的工作電壓最高可達(dá) ? 集成超低噪聲頻率合成器;

ADI

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Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 頁數(shù)：48 Pages

AD

亞德諾

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 頁數(shù)：48 Pages

AD

亞德諾

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 頁數(shù)：48 Pages

AD

亞德諾

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 頁數(shù)：48 Pages

AD

亞德諾

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 頁數(shù)：48 Pages

AD

亞德諾

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

文件：1.30363 Mbytes 頁數(shù)：48 Pages

AD

亞德諾

Low Jitter Clock Generator with Eight LVPECL Outputs

文件：852.11 Kbytes 頁數(shù)：48 Pages

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包裝：散裝 功能：時(shí)鐘發(fā)生器 類別：開發(fā)板，套件，編程器 評(píng)估和演示板及套件 描述：KIT EVAL FOR CRO29508

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