1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independe

文件：633.93 Kbytes 頁數(shù)：28 Pages

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1.6 GHz時(shí)鐘分配IC、分頻器、延遲調(diào)整、3路輸出

AD9514是一款多路輸出時(shí)鐘分配IC，具有低抖動(dòng)和低相位噪聲特性，有助于實(shí)現(xiàn)優(yōu)質(zhì)數(shù)據(jù)轉(zhuǎn)換器性能。這款器件也適合相位噪聲和抖動(dòng)要求嚴(yán)格的其它應(yīng)用。???\n\n 它提供3路獨(dú)立的時(shí)鐘輸出，其中2路為LVPECL，第3路輸出可設(shè)置為LVDS或CMOS電平。LVPECL輸出的工作頻率可達(dá)1.6 GHz，第3路輸出的工作頻率在LVDS模式下可達(dá)800 MHz，在CMOS模式下可達(dá)250 MHz。\n\n 每路輸出都具有可編程分頻器，可設(shè)置1至32的整數(shù)分頻比。一路時(shí)鐘輸出相對于另一路時(shí)鐘輸出的相位可通過分頻器相位選擇功能進(jìn)行設(shè)置，用作時(shí)序粗調(diào)。\n\n LVDS/CMO ? 1.6 GHz差分時(shí)鐘輸入\n\n? 3個(gè)可編程分頻器\n? 編程范圍：1至32\n\n? 用于輸出到輸出延遲粗調(diào)的相位選擇\n\n\n\n\n? 2路獨(dú)立的1.6 GHz LVPECL時(shí)鐘輸出\n? 加性寬帶輸出抖動(dòng)：225 fs rms;

ADI

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1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independe

文件：633.93 Kbytes 頁數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independe

文件：633.93 Kbytes 頁數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independe

文件：633.93 Kbytes 頁數(shù)：28 Pages

AD

亞德諾

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

GENERAL DESCRIPTION The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independe

文件：633.93 Kbytes 頁數(shù)：28 Pages

AD

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1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

文件：634.71 Kbytes 頁數(shù)：28 Pages

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包裝：盒 功能：時(shí)鐘分配 類別：開發(fā)板，套件，編程器 評估和演示板及套件 描述：BOARD EVAL CLOCK 3CH AD9514

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Package：32-VFQFN 裸露焊盤，CSP；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：IC CLK BUFFER 1:3 1.6GHZ 32LFCSP

AD

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Package：32-VFQFN 裸露焊盤，CSP；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：IC CLK BUFFER 1:3 1.6GHZ 32LFCSP

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