1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：1.19355 Mbytes 頁數(shù)：60 Pages

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：1.19355 Mbytes 頁數(shù)：60 Pages

AD

亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：1.19355 Mbytes 頁數(shù)：60 Pages

AD

亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：1.19355 Mbytes 頁數(shù)：60 Pages

AD

亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：1.19355 Mbytes 頁數(shù)：60 Pages

AD

亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：1.19355 Mbytes 頁數(shù)：60 Pages

AD

亞德諾

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this

文件：1.19355 Mbytes 頁數(shù)：60 Pages

AD

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1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

文件：1.19421 Mbytes 頁數(shù)：60 Pages

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Package：48-VFQFN 裸露焊盤，CSP；包裝：管件 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：IC CLK BUFFER 2:5 1.2GHZ 48LFCSP

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Package：48-VFQFN 裸露焊盤，CSP；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：IC CLK BUFFER 2:5 1.2GHZ 48LFCSP

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