1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential c

文件：838.3 Kbytes 頁數(shù)：40 Pages

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1.65 GHz Clock Fanout Buffer

文件：1.0097 Mbytes 頁數(shù)：40 Pages

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1.65 GHz時鐘扇出緩沖器，集成輸出分頻器和延遲調(diào)整

AD9508提供時鐘扇出能力，針對能使系統(tǒng)性能達到優(yōu)質(zhì)的低抖動進行設(shè)計。這款器件能滿足時鐘數(shù)據(jù)轉(zhuǎn)換器等應(yīng)用所需的相位噪聲和低抖動要求，可優(yōu)化這些應(yīng)用的性能。\n\n 它集成4個獨立的差分時鐘輸出，每一個輸出都支持多種邏輯電平類型。包括LVDS (1.65 GHz)、HSTL (1.65 GHz)和1.8 V CMOS (250 MHz)。在1.8 V CMOS輸出模式下，差分輸出轉(zhuǎn)換為兩個CMOS單端信號。無論工作電源電壓如何改變，CMOS輸出始終為1.8 V邏輯電平。 \n\n 每路輸出都有一個可編程分頻器，可以旁路該分頻器或者設(shè)置最高1024的整數(shù)分頻比。此外，AD95 ? 1.65 GHz差分時鐘輸入/輸出 \n\n? 10位可編程分頻器，1至1024整數(shù)分頻比 \n\n? 高達4個差分輸出或8個CMOS輸出 \n\n? 用于上電時進行硬連線編程的引腳綁定功能\n\n? 寬帶隨機抖動：<115 fs rms \n\n? 加性輸出抖動：41fs rms（12 KHz至20 MHz） \n\n? 出色的輸出間隔離\n\n? 所有輸出自動同步\n\n? 欲了解更多特性，請參考數(shù)據(jù)手冊;

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1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential c

文件：838.3 Kbytes 頁數(shù)：40 Pages

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1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential c

文件：838.3 Kbytes 頁數(shù)：40 Pages

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1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

GENERAL DESCRIPTION The AD9508 provides clock fanout capability in a design that emphasizes low jitter to maximize system performance. This device benefits applications like clocking data converters with demanding phase noise and low jitter requirements. There are four independent differential c

文件：838.3 Kbytes 頁數(shù)：40 Pages

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1.65 GHz Clock Fanout Buffer

文件：1.0097 Mbytes 頁數(shù)：40 Pages

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1.65 GHz Clock Fanout Buffer

文件：1.0097 Mbytes 頁數(shù)：40 Pages

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1.65 GHz Clock Fanout Buffer

文件：1.0097 Mbytes 頁數(shù)：40 Pages

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Package：24-WFQFN 裸露焊盤，CSP；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時鐘緩沖器，驅(qū)動器 描述：IC CLK BUFF 1:4 1.65GHZ 24LFCSP

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