MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

FEATURES Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassable DAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK inpu

文件：851.58 Kbytes 頁數(shù)：36 Pages

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MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

文件：717.33 Kbytes 頁數(shù)：33 Pages

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MxFE? 四通道 16 位 12GSPS RFDAC 和雙通道 12 位 6GSPS RFADC

混合信號前端(MxFE?) 是一款高度集成的器件，搭載16位、12 GSPS最大采樣速率的RF數(shù)模轉(zhuǎn)換器(DAC)內(nèi)核，以及12位、6 GSPS采樣速率的RF模數(shù)轉(zhuǎn)換器(ADC)內(nèi)核。AD9082支持4個發(fā)射器通道和2個接收器通道。AD9082非常適合需要使用寬帶ADC和DAC來處理具有寬瞬時帶寬的信號的應(yīng)用。該器件具有16通道、16.22 Gbps JESD204C或15.5 Gbps JESD204B數(shù)據(jù)收發(fā)器端口、片內(nèi)時鐘倍頻器和數(shù)字信號處理(DSP)功能，適合寬帶或多頻段直接至RF應(yīng)用。AD9082還具有旁路模式，允許ADC和/或DAC內(nèi)核的全寬帶功能旁路DSP數(shù)據(jù)路徑。此器件還具有低 ? 靈活、可重新配置的通用平臺設(shè)計\n? 4個DAC和2個ADC(4D2A)\n\n? 支持單通道、雙通道、四通道\n\n? 最大DAC/ADC采樣速率高達12 GSPS/6 GSPS\n? DAC至ADC的采樣速率比為1、2、3和4\n\n? ADC和DAC數(shù)據(jù)路徑旁路選項\n\n? 模擬帶寬高達8 GHz\n\n? 滿量程輸出電流范圍，交流耦合：7 mA至40 mA\n\n\n\n\n? 片內(nèi)PLL，支持多芯片同步\n? 外部RFCLK輸入選項\n\n\n\n\n\n\n\n? 6 GSPS時的ADC交流性能\n? 滿量程輸入電壓：1.475 V p-p\n\n? 滿量程正弦波輸入功率：4;

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亞德諾

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

FEATURES Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassable DAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK inpu

文件：851.58 Kbytes 頁數(shù)：36 Pages

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亞德諾

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

FEATURES Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassable DAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK inpu

文件：851.58 Kbytes 頁數(shù)：36 Pages

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亞德諾

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

FEATURES Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassable DAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK inpu

文件：851.58 Kbytes 頁數(shù)：36 Pages

AD

亞德諾

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

FEATURES Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassable DAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK inpu

文件：851.58 Kbytes 頁數(shù)：36 Pages

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亞德諾

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

FEATURES Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassable DAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK inpu

文件：851.58 Kbytes 頁數(shù)：36 Pages

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亞德諾

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

FEATURES Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassable DAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK inpu

文件：851.58 Kbytes 頁數(shù)：36 Pages

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亞德諾

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC

文件：717.33 Kbytes 頁數(shù)：33 Pages

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