Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

GENERAL DESCRIPTION The AD73571 is a dual, 14-bit, high speed, low power, successive approximation analog-to-digital converter (ADC) that operates from a single 2.5 V power supply and features throughput rates up to 4.2 MSPS. The part contains two ADCs, each preceded by a low noise, wide ban

文件：196.25 Kbytes 頁數(shù)：17 Pages

AD

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Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC

文件：398.43 Kbytes 頁數(shù)：20 Pages

AD

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Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC

文件：469.19 Kbytes 頁數(shù)：20 Pages

AD

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Differential Input, Dual, Simultaneous Sampling

文件：690.77 Kbytes 頁數(shù)：25 Pages

AD

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差分輸入、雙通道、同步采樣、4.25 MSPS、14 Bit、逐次逼近型（SAR）模數(shù)轉(zhuǎn)換器（ADC）

AD7357是一款雙通道、14 bit、高速、低功耗的逐次逼近型（SAR）模數(shù)轉(zhuǎn)換器（ADC），采用2.5 V單電源供電，具有高達(dá)4.25 MSPS的吞吐率。該器件內(nèi)置兩個(gè)ADC，各ADC之前均配有一個(gè)低噪聲、寬帶寬采樣保持電路，可處理110 MHz以上的輸入頻率。\n\n 轉(zhuǎn)換過程和數(shù)據(jù)采集使用標(biāo)準(zhǔn)控制輸入，易于與微處理器或數(shù)字信號處理器（DSP）進(jìn)行連接。其輸入信號在CS的下降沿采樣，同時(shí)轉(zhuǎn)換開始。轉(zhuǎn)換時(shí)間由SCLK頻率決定。\n\n AD7357采用先進(jìn)的設(shè)計(jì)技術(shù)，可在高吞吐速率下實(shí)現(xiàn)極低的功耗。它采用2.5 V電源供電，吞吐速率為4.25 MSPS，典型功耗為14 ? 雙通道14位SAR ADC\n\n? 同步采樣\n\n? 吞吐速率：每通道4.2 MSPS\n\n? 額定電壓(VDD)：2.5 V\n\n? 功耗：36 mW (4.25 MSPS);

ADI

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Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

GENERAL DESCRIPTION The AD73571 is a dual, 14-bit, high speed, low power, successive approximation analog-to-digital converter (ADC) that operates from a single 2.5 V power supply and features throughput rates up to 4.2 MSPS. The part contains two ADCs, each preceded by a low noise, wide ban

文件：196.25 Kbytes 頁數(shù)：17 Pages

AD

亞德諾

Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

GENERAL DESCRIPTION The AD73571 is a dual, 14-bit, high speed, low power, successive approximation analog-to-digital converter (ADC) that operates from a single 2.5 V power supply and features throughput rates up to 4.2 MSPS. The part contains two ADCs, each preceded by a low noise, wide ban

文件：196.25 Kbytes 頁數(shù)：17 Pages

AD

亞德諾

Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

GENERAL DESCRIPTION The AD73571 is a dual, 14-bit, high speed, low power, successive approximation analog-to-digital converter (ADC) that operates from a single 2.5 V power supply and features throughput rates up to 4.2 MSPS. The part contains two ADCs, each preceded by a low noise, wide ban

文件：196.25 Kbytes 頁數(shù)：17 Pages

AD

亞德諾

Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

GENERAL DESCRIPTION The AD73571 is a dual, 14-bit, high speed, low power, successive approximation analog-to-digital converter (ADC) that operates from a single 2.5 V power supply and features throughput rates up to 4.2 MSPS. The part contains two ADCs, each preceded by a low noise, wide ban

文件：196.25 Kbytes 頁數(shù)：17 Pages

AD

亞德諾

Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

GENERAL DESCRIPTION The AD73571 is a dual, 14-bit, high speed, low power, successive approximation analog-to-digital converter (ADC) that operates from a single 2.5 V power supply and features throughput rates up to 4.2 MSPS. The part contains two ADCs, each preceded by a low noise, wide ban

文件：196.25 Kbytes 頁數(shù)：17 Pages

AD

亞德諾