24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 μs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 頁(yè)數(shù)：63 Pages

AD

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24-Bit, 250 kSPS, Sigma-Delta ADC Settling and True Rail-to-Rail Buffers

文件：1.11819 Mbytes 頁(yè)數(shù)：63 Pages

AD

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Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier

文件：1.05142 Mbytes 頁(yè)數(shù)：59 Pages

AD

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24位、250 KSPS Σ-Δ型ADC，具有20 MS建立時(shí)間和真軌到軌緩沖器

AD7175-2是一款低噪聲、快速建立、多路復(fù)用、2/4通道（全差分/偽差分）Σ-Δ型模數(shù)轉(zhuǎn)換器(ADC)，適合低帶寬輸入。針對(duì)完全建立的數(shù)據(jù)，該器件最大通道掃描速率為50 kSPS (20 μs)。該器件的輸出數(shù)據(jù)速率范圍為5 SPS至250 kSPS。\n\n AD7175-2集成關(guān)鍵的模擬和數(shù)字信號(hào)調(diào)理模塊，可讓用戶針對(duì)使用的每個(gè)模擬輸入通道單獨(dú)進(jìn)行配置。用戶可為各通道單獨(dú)選擇功能。模擬輸入端和外部基準(zhǔn)電壓輸入端的集成真軌到軌緩沖器可提供易于驅(qū)動(dòng)的高阻抗輸入。精密2.5 V低漂移(2 ppm/癈)帶隙內(nèi)部基準(zhǔn)電壓源（帶輸出基準(zhǔn)電壓源緩沖器）增加了嵌入式功能，同時(shí)減少了外部元件數(shù) ? 快速且靈活的輸出速率：5 SPS至250 kSPS\n\n? 通道掃描速率：50 kSPS/通道（20 μs建立時(shí)間）\n\n? 性能規(guī)格\n? 17.2位無(wú)噪聲分辨率(250 kSPS)\n\n? 20位無(wú)噪聲分辨率(2.5 kSPS)\n\n? 24位無(wú)噪聲分辨率(20 SPS)\n\n? 積分非線性(INL)：FSR的±1 ppm\n\n\n\n\n? 50 Hz和60 Hz抑制：85 dB，建立時(shí)間為50 ms\n\n? 用戶可配置的輸入通道\n? 2個(gè)全差分通道或4個(gè)單端通道\n\n? 交叉點(diǎn)多路復(fù)用器\n\n\n\n\n? 2.5 V片內(nèi)基準(zhǔn)電壓源（±2 ppm/°C漂移）\n;

ADI

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24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 μs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 頁(yè)數(shù)：63 Pages

AD

亞德諾

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 μs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 頁(yè)數(shù)：63 Pages

AD

亞德諾

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 μs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 頁(yè)數(shù)：63 Pages

AD

亞德諾

24-Bit, 250 kSPS, Sigma-Delta ADC Settling and True Rail-to-Rail Buffers

文件：1.11819 Mbytes 頁(yè)數(shù)：63 Pages

AD

亞德諾

24-Bit, 250 kSPS, Sigma-Delta ADC Settling and True Rail-to-Rail Buffers

文件：1.11819 Mbytes 頁(yè)數(shù)：63 Pages

AD

亞德諾

24-Bit, 250 kSPS, Sigma-Delta ADC Settling and True Rail-to-Rail Buffers

文件：1.11819 Mbytes 頁(yè)數(shù)：63 Pages

AD

亞德諾