低抖動(dòng)時(shí)鐘發(fā)生器

AC1571 是用于 5G 基站應(yīng)用的基于 PLL 的時(shí)鐘發(fā)生器，該芯片采用全數(shù)字鎖相環(huán)技術(shù)，以實(shí)現(xiàn)最佳的高頻低相噪性能，并具有低功耗和高 PSRR 能力。AC1571 使用 ADPLL 技術(shù)，可實(shí)現(xiàn)<0.3ps RMS 的相位抖動(dòng)性能。\nAC1571 輸出差分 100MHz，125MHz，156.25MHz 和單端 33.33MHz CPU 時(shí)鐘，同時(shí)六個(gè) LVCMOS 輸出還用作 25MHz 晶振參考的驅(qū)動(dòng)扇出。 ? 七路單端LVCMOS輸出，輸出阻抗為30歐姆；\n? 1路單端LVCMOS（QD0）33.33MHz CPU時(shí)鐘；\n? 晶體振蕩器接口設(shè)計(jì)用于25MHz并聯(lián)諧振晶體；\n? 125MHz下的RMS相位抖動(dòng)，使用25MHz晶體（12kHz–20MHz）：0.27ps（典型）；\n? 3.3 v電源電壓；\n? 無(wú)鉛（RoHS 6）封裝；;

SAISI

賽思

5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers

DESCRIPTION The AIC1571 combines a synchronous voltage mode controller with two linear controllers as well as the monitoring and protection functions in this chip. The PWM controller regulates the microprocessor core voltage with a synchronous rectified buck converter. One linear controller regul

文件：462.6 Kbytes 頁(yè)數(shù)：18 Pages

AIC

沛亨半導(dǎo)體

5-bit DAC, Synchronous PWM Power Regulator with Dual Linear Controllers

DESCRIPTION The AIC1571 combines a synchronous voltage mode controller with two linear controllers as well as the monitoring and protection functions in this chip. The PWM controller regulates the microprocessor core voltage with a synchronous rectified buck converter. One linear controller regul

文件：462.6 Kbytes 頁(yè)數(shù)：18 Pages

AIC

沛亨半導(dǎo)體

Guards against accidental disconnection of Computers, PDU’s, Servers and most Network Devices.

文件：5.42821 Mbytes 頁(yè)數(shù)：7 Pages

BURLAND