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          型號(hào)下載 訂購功能描述制造商 上傳企業(yè)LOGO

          SN74ABT827DBR

          絲?。?strong>AB827;Package:SSOP;10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.58 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827DBR

          絲印:AB827;Package:SSOP(DB);10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.94 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827DBR.B

          絲?。?strong>AB827;Package:SSOP(DB);10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.94 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827DBR.B

          絲?。?strong>AB827;Package:SSOP;10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.58 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827PW

          絲?。?strong>AB827;Package:TSSOP;10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.58 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827PW

          絲印:AB827;Package:TSSOP(PW);10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.94 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827PW.B

          絲印:AB827;Package:TSSOP(PW);10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.94 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827PW.B

          絲?。?strong>AB827;Package:TSSOP;10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.58 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827PWR

          絲?。?strong>AB827;Package:TSSOP;10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.58 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          SN74ABT827PWR

          絲?。?strong>AB827;Package:TSSOP(PW);10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

          State-of-the-Art EPIC-ΙΙB? BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

          文件:519.94 Kbytes 頁數(shù):19 Pages

          TI

          德州儀器

          供應(yīng)商型號(hào)品牌批號(hào)封裝庫存備注價(jià)格
          TexasInstruments
          18+
          ICBUFF/DVRTRI-ST10BIT24T
          6800
          公司原裝現(xiàn)貨/歡迎來電咨詢!
          詢價(jià)
          TI
          24+
          60
          詢價(jià)
          Texas Instruments
          24+
          24-TSSOP
          65200
          一級(jí)代理/放心采購
          詢價(jià)
          TI
          25+
          SSOP-24
          360
          就找我吧!--邀您體驗(yàn)愉快問購元件!
          詢價(jià)
          TI(德州儀器)
          2021+
          TSSOP-24
          499
          詢價(jià)
          TI
          22+
          24TSSOP
          9000
          原廠渠道,現(xiàn)貨配單
          詢價(jià)
          Texas Instruments(德州儀器)
          24+
          SOIC-16
          690000
          代理渠道/支持實(shí)單/只做原裝
          詢價(jià)
          Texas Instruments
          25+
          24-TSSOP(0.173 4.40mm 寬)
          9350
          獨(dú)立分銷商 公司只做原裝 誠心經(jīng)營 免費(fèi)試樣正品保證
          詢價(jià)
          TI
          25+
          TSSOP-24
          18746
          樣件支持,可原廠排單訂貨!
          詢價(jià)
          TI
          25+
          TSSOP-24
          18798
          正規(guī)渠道,免費(fèi)送樣。支持賬期,BOM一站式配齊
          詢價(jià)
          更多AB827供應(yīng)商 更新時(shí)間2026-1-19 16:39:00
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