DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER

FEATURES ■ Controlled Output Slew Rate ■ High-Speed Data Storage ■ 60 V Minimum ■ High Data Input Rate Output Breakdown ■ Low Output-Saturation Voltages ■ PNP Active Pull-Downs ■ Improved Replacements ■ Low-Power CMOS Logic for SN75518N, SN75518NF, and Latches UCN5818–, and UCQ5818–

文件：124.88 Kbytes 頁數(shù)：7 Pages

ALLEGRO

Controlled output slew rate

The A6818– devices combine a 32-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and - 40 mA output ratings also allow these devices to be used in many

文件：266.15 Kbytes 頁數(shù)：7 Pages

ALLEGRO

Package：44-LCC（J 形引線）；包裝：卷帶（TR） 類別：集成電路（IC） 配電開關，負載驅動器 描述：IC PWR DRVR BIPOLAR 1:32 44PLCC

ALLEGRO

DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER

FEATURES ■ Controlled Output Slew Rate ■ High-Speed Data Storage ■ 60 V Minimum ■ High Data Input Rate Output Breakdown ■ Low Output-Saturation Voltages ■ PNP Active Pull-Downs ■ Improved Replacements ■ Low-Power CMOS Logic for SN75518N, SN75518NF, and Latches UCN5818–, and UCQ5818–

文件：124.88 Kbytes 頁數(shù)：7 Pages

ALLEGRO

DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER

FEATURES ■ Controlled Output Slew Rate ■ High-Speed Data Storage ■ 60 V Minimum ■ High Data Input Rate Output Breakdown ■ Low Output-Saturation Voltages ■ PNP Active Pull-Downs ■ Improved Replacements ■ Low-Power CMOS Logic for SN75518N, SN75518NF, and Latches UCN5818–, and UCQ5818–

文件：124.88 Kbytes 頁數(shù)：7 Pages

ALLEGRO

DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER

FEATURES ■ Controlled Output Slew Rate ■ High-Speed Data Storage ■ 60 V Minimum ■ High Data Input Rate Output Breakdown ■ Low Output-Saturation Voltages ■ PNP Active Pull-Downs ■ Improved Replacements ■ Low-Power CMOS Logic for SN75518N, SN75518NF, and Latches UCN5818–, and UCQ5818–

文件：124.88 Kbytes 頁數(shù)：7 Pages

ALLEGRO