1M X 18, 512K X 36 LVTTL, Flow-through ZeBL? SRAM

General Description\nThe AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.\nThe A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAM ■ Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz)\n■ Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization\n■ Signal +3.3V ± 5% power supply\n■ Individual Byte Write control capability\n■ Clock enable ( CEN) pin to enable clock and suspend operations\n■ Clock-contro;

AMIC

聯(lián)笙電子