Universal-Input/15 W 50 kHz Flyback Switching Regulators

FEATURES AND BENEFITS ■ 50 kHz PWM with ±5 Frequency Jittering Cost Reduction of EMI Noise Filtering ■ Rugged 650 V Avalanche-Rated MOSFET Simplified Surge Absorption No VDSS Derating Required ■ Choice of rDS(on) (2.8 Ω or 3.95 Ω maximum) ■ Auto-Burst Mode for Stand-By Operation or Light Lo

文件：373.27 Kbytes 頁(yè)數(shù)：7 Pages

ALLEGRO

Universal-Input/15 W 67 kHz Flyback Switching Regulator

FEATURES AND BENEFITS ■ 67 kHz PWM with ±5 Frequency Jittering Cost Reduction of EMI Noise Filtering ■ Rugged 650 V Avalanche-Rated MOSFET Simplified Surge Absorption No VDSS Derating Required ■ Low rDS(on) (3.95 Ω maximum) ■ Auto-Burst Mode for Stand-By Operation or Light Loads Less Trans

文件：327.33 Kbytes 頁(yè)數(shù)：7 Pages

ALLEGRO

16-ch Isolated Digital Input Modbus TCP Module

文件：1.62858 Mbytes 頁(yè)數(shù)：2 Pages

ADVANTECH

研華科技

AM62x Sitara? Processors

1 Features Processor Cores: ? Up to Quad 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Single-core A

文件：5.30504 Mbytes 頁(yè)數(shù)：259 Pages

TI

德州儀器

AM62x Sitara??Processors

1 Features Processor Cores: ? Up to Quad 64-bit Arm? Cortex?-A53 microprocessor subsystem at up to 1.4 GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection ? Single-core A

文件：5.83552 Mbytes 頁(yè)數(shù)：235 Pages

TI

德州儀器