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                >9FGV0441>規(guī)格書列表
                
    
            
    
                
    
                    
    型號下載 訂購功能描述制造商 上傳企業(yè)LOGO
    
                    
    9FGV0441
    Programmable Slew rate for each output
    
Description
The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo = 100?. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

    文件：230.97 Kbytes 頁數(shù)：15 Pages
    IDT
    

    9FGV0441
    4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
    
Features/Benefits
? Integrated terminations provide 100? differential Zo;
reduced component count and board space
? 1.8V operation; reduced power consumption
? OE# pins; support DIF power management
? LP-HCSL differential clock outputs; reduced power and
board space
? Programmable slew rate
    文件：688.57 Kbytes 頁數(shù)：17 Pages
    RENESAS
    瑞薩
    

    9FGV0441
    4-output 1.8V PCIe Gen1-4 Clock Generator with Zo = 100 ohms
    The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen1–4?applications with integrated output terminations providing Zo = 100Ω. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.  Integrated terminations provide 100Ω differential Zo; reduced component count and board space\n1.8V operation; reduced power consumption\nOE# pins; support DIF power management\nLP-HCSL differential clock outputs; reduced power and board space\nProgrammable slew rate for each output; allows tuning f;
    Renesas
    瑞薩
    

    9FGV0441AKILF
    絲印：ICSV0441AIL；Package：32-VFQFPN；4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
    
Features/Benefits
? Integrated terminations provide 100? differential Zo;
reduced component count and board space
? 1.8V operation; reduced power consumption
? OE# pins; support DIF power management
? LP-HCSL differential clock outputs; reduced power and
board space
? Programmable slew rate
    文件：688.57 Kbytes 頁數(shù)：17 Pages
    RENESAS
    瑞薩
    

    9FGV0441AKILFT
    絲?。?a target="_blank" title="Marking" href="/icsv0441ail/marking.html">ICSV0441AIL；Package：32-VFQFPN；4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
    
Features/Benefits
? Integrated terminations provide 100? differential Zo;
reduced component count and board space
? 1.8V operation; reduced power consumption
? OE# pins; support DIF power management
? LP-HCSL differential clock outputs; reduced power and
board space
? Programmable slew rate
    文件：688.57 Kbytes 頁數(shù)：17 Pages
    RENESAS
    瑞薩
    

    9FGV0441AKLF
    絲?。?a target="_blank" title="Marking" href="/icsv0441ail/marking.html">ICSV0441AIL；Package：32-VFQFPN；4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
    
Features/Benefits
? Integrated terminations provide 100? differential Zo;
reduced component count and board space
? 1.8V operation; reduced power consumption
? OE# pins; support DIF power management
? LP-HCSL differential clock outputs; reduced power and
board space
? Programmable slew rate
    文件：688.57 Kbytes 頁數(shù)：17 Pages
    RENESAS
    瑞薩
    

    9FGV0441AKLFT
    絲?。?a target="_blank" title="Marking" href="/icsv0441ail/marking.html">ICSV0441AIL；Package：32-VFQFPN；4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
    
Features/Benefits
? Integrated terminations provide 100? differential Zo;
reduced component count and board space
? 1.8V operation; reduced power consumption
? OE# pins; support DIF power management
? LP-HCSL differential clock outputs; reduced power and
board space
? Programmable slew rate
    文件：688.57 Kbytes 頁數(shù)：17 Pages
    RENESAS
    瑞薩
    

    9FGV0441_17
    4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
    文件：294.55 Kbytes 頁數(shù)：16 Pages
    IDT
    

    9FGV0441AKILF
    4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
    文件：294.55 Kbytes 頁數(shù)：16 Pages
    IDT
    

    9FGV0441AKILFT
    4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
    文件：294.55 Kbytes 頁數(shù)：16 Pages
    IDT
    

    
            
    
		
        
    
            
    
                
    技術參數(shù)
    
            
    
            
      
            	
    • Architecture：
      Common
    • App Jitter Compliance：
      PCIe Gen1
    • Diff. Outputs：
      4
    • Diff. Output Signaling：
      LP-HCSL
    • Output Impedance：
      100
    • Power Consumption Typ (mW)：
      58
    • Supply Voltage (V)：
      1.8
    • Advanced Features：
      Reference Output
    • Lead Count (#)：
      32
    • Pkg. Type：
      VFQFPN
    • Pkg. Dimensions (mm)：
      5.0 x 5.0 x 0.9
    
            
    
        
    
            
    供應商型號品牌批號封裝庫存備注價格
    
                
    



    IDT, Integrated Device Technol
    		

    24+
    		

    32-VFQFPN(5x5)
    		

    53200
    		

    一級代理/放心采購
    		
詢價
    

    



    IDT
    		

    1931+
    		

    N/A
    		

    650
    		

    加我qq或微信，了解更多詳細信息,體驗一站式購物
    		
詢價
    

    



    RENESAS(瑞薩)/IDT
    		

    2447
    		

    VFQFPN-32(5x5)
    		

    315000
    		

    一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨
    		
詢價
    

    



    IDT
    		

    25+
    		

    QFN-32
    		

    3854
    		

    就找我吧!--邀您體驗愉快問購元件!
    		
詢價
    

    



    RENESAS(瑞薩)/IDT
    		

    2021+
    		

    VFQFPN-32(5x5)
    		

    499
    		

    		
詢價
    

    



    IDT
    		

    23+
    		

    QFN
    		

    50000
    		

    全新原裝正品現(xiàn)貨,支持訂貨
    		
詢價
    

    



    IDT
    		

    22+
    		

    NA
    		

    650
    		

    加我QQ或微信咨詢更多詳細信息,
    		
詢價
    

    



    IDT
    		

    22+
    		

    32VFQFPN
    		

    9000
    		

    原廠渠道,現(xiàn)貨配單
    		
詢價
    

    



    IDT
    		

    23+
    		

    32-VFQFPN
    		

    3000
    		

    一級代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、
    		
詢價
    

    



    IDT
    		

    1433+
    		

    32-VFQFPN
    		

    65
    		

    一級代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力
    		
詢價
    

            
    
        
    
        
    更多9FGV0441供應商
            更新時間2026-1-22 14:27:00
        
    
        
    
          
    
            
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