2-Output 1.8V PCIe Zero Delay/Fanout Clock Buffer with Zo = 100ohms

Description The 9DBV0241 is a member of Renesas' 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. Features/Benefits ? LP-HCSL outputs with Zo = 100?; saves 8 resistors compared to standard HCSL outputs ? 35mW typical power consumption in PLL mod

文件：756.12 Kbytes 頁數(shù)：17 Pages

RENESAS

瑞薩

slew rate for each output

文件：311.19 Kbytes 頁數(shù)：17 Pages

ICST

2-Output 1.8V PCIe Gen1/2/3 Zero Delay

文件：312.64 Kbytes 頁數(shù)：17 Pages

IDT

SMBus-selectable features

文件：311.27 Kbytes 頁數(shù)：17 Pages

IDT

2-output 1.8V PCIe Zero-Delay/Fanout Clock Buffer

The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management. LP-HCSL outputs with Zo=100Ω; saves 8 resistors compared to standard HCSL output\n35mW typical power consumption in PLL mode; minimal power consumption\nSpread Spectrum (SS) compatible; allows use of SS for EMI reduction\nOE# pins; support DIF power management\nHCSL compatible differential input; ca;

Renesas

瑞薩

2-Output 1.8V PCIe Gen1/2/3 Zero Delay

文件：312.64 Kbytes 頁數(shù)：17 Pages

IDT

2-Output 1.8V PCIe Gen1/2/3 Zero Delay

文件：312.64 Kbytes 頁數(shù)：17 Pages

IDT

2-Output 1.8V PCIe Gen1/2/3 Zero Delay

文件：312.64 Kbytes 頁數(shù)：17 Pages

IDT

2-Output 1.8V PCIe Gen1/2/3 Zero Delay

文件：312.64 Kbytes 頁數(shù)：17 Pages

IDT

2-Output 1.8V PCIe Gen1/2/3 Zero Delay

文件：312.64 Kbytes 頁數(shù)：17 Pages

IDT