6-output 3.3V PCIe Zero-Delay Buffer

文件：307.82 Kbytes 頁數(shù)：19 Pages

IDT

6-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer

The 9DBL0641 6-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0641 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures. ? Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)\n? PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode)\n? 6 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair\n? Direct connection to 100Ω transmission lines\n? Dedicated OE# pin for each output\n? Spread Spectrum tolerant\;

Renesas

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6-output 3.3V PCIe Zero-Delay Buffer

文件：307.82 Kbytes 頁數(shù)：19 Pages

IDT

6-output 3.3V PCIe Zero-Delay Buffer

文件：318.63 Kbytes 頁數(shù)：19 Pages

IDT

6-output 3.3V PCIe Zero-Delay Buffer

文件：307.82 Kbytes 頁數(shù)：19 Pages

IDT

6-output 3.3V PCIe Zero-Delay Buffer

文件：318.63 Kbytes 頁數(shù)：19 Pages

IDT

Package：40-VFQFN 裸露焊盤；包裝：管件 類別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：IC CLK FANOUT/BUFF ZD 40VFQFPN

Renesas Electronics America Inc

Package：40-VFQFN 裸露焊盤；包裝：卷帶（TR） 類別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：VFQFPN 5.00X5.00X0.90 MM, 0.40MM

Renesas Electronics America Inc