4-Output 3.3V PCIe Zero-delay Buffer

文件：305.09 Kbytes 頁數(shù)：19 Pages

IDT

4-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer

The 9DBL0452 4-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0452 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.\n\nFor information regarding evaluation boards and material, please contact your local?s ? Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)\n? 4 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair\n? Dedicated OE# pin for each output\n? Pin or SMBus configuration\n? SMBus interface not required for device operation\n? Space saving 32-pin 5 × 5 mm VFQFPN;

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4-output 3.3V PCIe Zero-delay Buffer

文件：305.76 Kbytes 頁數(shù)：19 Pages

IDT

4-Output 3.3V PCIe Zero-delay Buffer

文件：305.09 Kbytes 頁數(shù)：19 Pages

IDT

4-Output 3.3V PCIe Zero-delay Buffer

文件：305.09 Kbytes 頁數(shù)：19 Pages

IDT

4-output 3.3V PCIe Zero-delay Buffer

文件：305.76 Kbytes 頁數(shù)：19 Pages

IDT

Package：32-VFQFN 裸露焊盤；包裝：管件 類別：集成電路（IC） 應用特定時鐘/定時 描述：IC CLK BUFFER ZD 32-VFQFPN

Renesas Electronics America Inc

Package：32-VFQFN 裸露焊盤；包裝：卷帶（TR） 類別：集成電路（IC） 應用特定時鐘/定時 描述：IC CLK BUFFER ZD 32-VFQFPN

Renesas Electronics America Inc