Low Cost DDR Phase Lock Loop Zero Delay Buffer

Description Output Features DDR Zero Delay Clock Buffer ? Low skew, low jitter PLL clock driver ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? 3.3V tolerant CLK_INT input Key Specifications ? PEAK - PEAK jitt

文件：240.76 Kbytes 頁數(shù)：8 Pages

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DDR Zero Delay Clock Buffer

DDR Zero Delay Clock Buffer Low skew, low jitter PLL clock driver\nI2C for functional and output control\nFeedback pins for input to output synchronization\nSpread Spectrum tolerant inputs\n3.3V tolerant CLK_INT input;

Renesas

瑞薩

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: ? Low skew, low jitter PLL clock driver ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? 3.3V tolerant CLK_INT input Switching Characteristics: ? PEAK - PEAK jitter (66MHz):

文件：54.59 Kbytes 頁數(shù)：6 Pages

ICST

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: ? Low skew, low jitter PLL clock driver ? I2C for functional and output control ? Feedback pins for input to output synchronization ? Spread Spectrum tolerant inputs ? 3.3V tolerant CLK_INT input Switching Characteristics: ? PEAK - PEAK jitter (66MHz):

文件：54.59 Kbytes 頁數(shù)：6 Pages

ICST