VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

文件：310.32 Kbytes 頁數(shù)：9 Pages

IDT

VIDEO GENLOCK PLL

Features ? Phase-detector/VCO circuit block ? Ideal for genlock system ? Reference clock range 12 kHz to 1 MHz for full output clock range ? Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions ? O

文件：361.5 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩

VIDEO GENLOCK PLL

Features ? Phase-detector/VCO circuit block ? Ideal for genlock system ? Reference clock range 12 kHz to 1 MHz for full output clock range ? Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions ? O

文件：361.5 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

文件：310.32 Kbytes 頁數(shù)：9 Pages

IDT

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

文件：310.32 Kbytes 頁數(shù)：9 Pages

IDT

VIDEO GENLOCK PLL

Features ? Phase-detector/VCO circuit block ? Ideal for genlock system ? Reference clock range 12 kHz to 1 MHz for full output clock range ? Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions ? O

文件：361.5 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩

VIDEO GENLOCK PLL

Features ? Phase-detector/VCO circuit block ? Ideal for genlock system ? Reference clock range 12 kHz to 1 MHz for full output clock range ? Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions ? O

文件：361.5 Kbytes 頁數(shù)：10 Pages

RENESAS

瑞薩

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

文件：310.32 Kbytes 頁數(shù)：9 Pages

IDT

Piezoelectric load cells SlimLine Piezoelectric force transducers for tensile and compression forces of up to –20 ... 75 kN

? Calibrated force transducer ? Compact design, very small dimensions ? Integrated, non-detachable cable with fluoroelastomer sheath ? Plug coupling with mounting plate

文件：313.43 Kbytes 頁數(shù)：3 Pages

KSL

AMP Dynamic Series Connectors

文件：2.64998 Mbytes 頁數(shù)：43 Pages

MACOM