8A34005中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

描述 Description

The 8A34005 is a Synchronization Management Unit (SMU) for packet based and physical layer based equipment synchronization. The

8A34005 is a highly integrated device that provides tools to manage timing references, clock sources, and timing paths for IEEE 1588

and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators,

Digitally Controlled Oscillators (DCO) or Digital Phase Lock Loops (DPLL).

The 8A34005 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input,

input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly

synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces, as well

as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

Typical Applications

? Core and access IP switches / routers

? Synchronous Ethernet equipment

? Telecom Boundary Clocks (T-BCs) and Telecom Time Slave

Clocks (T-TSCs) according to ITU-T G.8273.2

? 10Gb, 40Gb, and 100Gb Ethernet interfaces

? Central Office Timing Source and Distribution

? Wireless infrastructure for 4.5G and 5G network equipment

特性 Features

? Four independent timing channels

? Each can act as a frequency synthesizer, jitter attenuator,

Digitally Controlled Oscillator (DCO), or Digital Phase Lock

Loop (DPLL)

? DPLLs generate telecom compliant clocks

? Compliant with ITU-T G.8262 for Synchronous Ethernet

? Compliant with ITU-T G.8262.1 for enhanced

Synchronous Ethernet

? Compliant with legacy SONET/SDH and PDH

requirements

? DPLL Digital Loop Filters (DLFs) are programmable with cut

off frequencies from 0.09mHz to 12kHz

? DPLL/DCO channels share frequency information using the

Combo Bus to simplify compliance with ITU-T G.8273.2

? Switching between DPLL and DCO modes is hitless and

dynamic

? Automatic reference switching between DCO and DPLL

modes to simplify support for an external phase/time input

interface in a T-BC

? Generates output frequencies that are independent of input

frequencies via a Fractional Output Divider (FOD)

? Each FOD supports output phase tuning with 1ps resolution