1-to-5 Differential-to-3.3V LVPECL PLL Clock Driver W/Dynamic Clock Switch

FEATURES ? Five differential 3.3V LVPECL outputs ? Selectable differential clock inputs ? CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? Output frequency range: 50MHz to 250MHz ? VCO range: 200MHz to 500MHz ? External feedback for “ze

文件：427.5 Kbytes 頁數(shù)：18 Pages

RENESAS

瑞薩

1-to-5 Differential-to-3.3V LVPECL PLL Clock Driver W/Dynamic Clock Switch

The 87993I is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signal frequency and phase while the other ·5 differential 3.3V LVPECL outputs\n·Selectable differential clock inputs\n·CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n·Output frequency range: 50MHz to 250MHz\n·VCO range: 200MHz to 500MHz\n·External feedback for \"zero delay\" clock rege;

Renesas

瑞薩

1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

文件：186.48 Kbytes 頁數(shù)：16 Pages

ICST

1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

文件：186.48 Kbytes 頁數(shù)：16 Pages

ICST

1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

文件：186.48 Kbytes 頁數(shù)：16 Pages

ICST