Differential-to-LVDS/0.7V Differential PCI Express? Jitter Attenuator

General Description The 8741004 is a high performance Differential-to-LVDS/0.7V Differential Jitter Attenuator designed for use in PCI Express? systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise

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Differential-to-LVDS/0.7V Differential PCI Express? Jitter Attenuator

The 8741004 is a high performance Differential-to-LVDS/0.7V Differential Jitter Attenuator designed for use in PCI Express?? systems. In some PCI Express? systems, such as those found in desktop PCs, the PCI Express? clocks are generated from a low bandwidth, high phase noise PLL frequency synthesiz ·Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs\n·One differential clock input pair\n·CLK, CLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n·Output frequency range: 98MHz;

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絲?。?a target="_blank" title="Marking" href="/ics8741004bil/marking.html">ICS8741004BIL；Package：TSSOP；Differential-to-LVDS/0.7V Differential PCI Express? Jitter Attenuator

Features ? Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs ? One differential clock input pair ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Output fr

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絲印：ICS8741004BIL；Package：TSSOP；Differential-to-LVDS/0.7V Differential PCI Express? Jitter Attenuator

Features ? Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs ? One differential clock input pair ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Output fr

文件：633.46 Kbytes 頁數(shù)：23 Pages

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Differential-to-LVDS/0.7V Differential PCI Express? Jitter Attenuator

Features ? Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs ? One differential clock input pair ? CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? Output fr

文件：633.46 Kbytes 頁數(shù)：23 Pages

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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS??JITTER ATTENUATOR

文件：1.31377 Mbytes 頁數(shù)：19 Pages

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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS??JITTER ATTENUATOR

文件：1.31377 Mbytes 頁數(shù)：19 Pages

IDT

DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS??JITTER ATTENUATOR

文件：1.31377 Mbytes 頁數(shù)：19 Pages

IDT

DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS??JITTER ATTENUATOR

文件：1.31377 Mbytes 頁數(shù)：19 Pages

IDT

DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS??JITTER ATTENUATOR

文件：1.99353 Mbytes 頁數(shù)：20 Pages

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