Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

GENERAL DESCRIPTION The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT. The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are

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RENESAS

瑞薩

Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

文件：339.51 Kbytes 頁(yè)數(shù)：21 Pages

IDT

LVPECL FemtoClock Dynamic Clock Switch/Generator

The 873996 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the HiPerClockS? family of low jitter/phase noise devices from IDT. The 873996 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical. The ·Six differential 3.3V LVPECL outputs\n·Selectable differential clock inputs\n·CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n·Input clock frequency range: 49MHz to 213.33MHz\n·Output clock frequency range: 49MHz to 640MHz\n·VCO range: 490MHz t;

Renesas

瑞薩

絲?。?a target="_blank" title="Marking" href="/ics873996ayl/marking.html">ICS873996AYL；Package：TQFP；Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

文件：339.51 Kbytes 頁(yè)數(shù)：21 Pages

IDT

絲?。?a target="_blank" title="Marking" href="/ics873996ayl/marking.html">ICS873996AYL；Package：TQFP；Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

文件：339.51 Kbytes 頁(yè)數(shù)：21 Pages

IDT

Package：48-TQFP 裸露焊盤(pán)；包裝：卷帶（TR） 類別：集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器 描述：IC ZD/MULT/DIVIDER 48-LQFP

Renesas Electronics America Inc

Package：48-TQFP 裸露焊盤(pán)；包裝：卷帶（TR） 類別：集成電路（IC） 時(shí)鐘發(fā)生器，PLL，頻率合成器 描述：IC ZD/MULT/DIVIDER 48-LQFP

Renesas Electronics America Inc