÷1/÷2 Differential-to-LVPECL Clock Generator

The 87321I is a high performance ÷1, ÷2 Differential-to-LVPECL Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The 87321I is characterized to operate from a 3.3V or 2.5V power supply. Guar ·One differential LVPECL output\n·One CLK, nCLK input pair\n·CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL\n·Maximum clock input frequency: 700MHz\n·Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias;

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Low Skew, ÷1/÷2,3.3V LVPECL /ECLClock Generator

The 87322BI is a low skew, ÷1/÷2 3.3V LVPECL/ECL Clock Generator. Using multiplexed/redundant clock inputs the 87322BI is designed to translate most differential signal levels to LVPECL/ECL levels. The CLK_SEL input selects between CLK0, nCLK0 and CLK1, nCLK1 as the active input. The divide select i ·Fifteen differential LVPECL outputs\n·Selectable LVPECL differential clock inputs\n·CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL\n·Output frequency: 750MHz (maximum)\n·Output skew: 180ps (maximum)\n·Bank skew: 65ps (maximum)\n·Part-to-part ;

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包裝：散裝 類別：標(biāo)簽，標(biāo)志，護(hù)欄，標(biāo)識 標(biāo)簽 描述：TAG BRASS RND 1.5 DHWR 226-250

Brady Corporation