Differential-To-HSTL Zero Delay Clock Generator

Features ? One differential HSTL output pair? One differential feedback output pair ? Differential CLK, nCLK input pair ? CLK, nCLK pair can accept the following differential ? input levels: LVPECL, LVDS, HSTL, HCSL, SSTL ? Output frequency range: 31.25MHz to 630MHz ? Input frequency range:

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Differential to HSTL Zero Delay Buffer Clock Generator

The 8725B-21 is a highly versatile 1:1 Differential-to-HSTL Clock Generator. The CLK, nCLK pair can accept most standard differential input levels. The 8725B-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz ? One differential HSTL output pairOne differential feedback output pair\n? Differential CLK, nCLK input pair\n? CLK, nCLK pair can accept the following differentialinput levels: LVPECL, LVDS, HSTL, HCSL, SSTL\n? Output frequency range: 31.25MHz to 630MHz\n? Input frequency range: 31.25MHz to 630MHz;

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QFN

IDT

上傳：深圳市鼎欣微電子有限公司

MOLEX

莫仕

上傳：深圳閱創(chuàng)想電子實(shí)業(yè)有限公司

MOLEX

莫仕

上傳：深圳閱創(chuàng)想電子實(shí)業(yè)有限公司