Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator

FEATURES ? Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance ? Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs ? CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL ? CLK0 input accepts LVCMOS or LVTTL input levels ? Output frequenc

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RENESAS

瑞薩

Output frequency range

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IDT

Zero Delay, Differential-to-LVCMOS/LVTTL Clock Generator

The 8705I is a highly versatile 1:8 Differential-to- LVCMOS/LVTTL Clock Generator. The 8705I has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The 8705I has a fully integrated PLL ·Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance\n·Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs\n·CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL\n·CLK0 input accepts LVCMOS or LVTTL input levels\n·Output frequency range: 15.625MHz;

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Amorphous Solar Cell

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SANYO

三洋

SERIAL 10-GBE/FIBRE CHANNEL TRANSCEIVER WITH WIS LAYER AND

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BOARDCOM

博通

SERIAL 10-GBE/FIBRE CHANNEL TRANSCEIVER WITH WIS LAYER AND

文件：99.87 Kbytes 頁數(shù)：2 Pages

BOARDCOM

博通