絲?。?a target="_blank" title="Marking" href="/ics87008agi/marking.html">ICS87008AGI；Package：TSSOP；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES ? Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) ? Selectable differential CLK1, nCLK1 or LVCMOS clock input ? CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Maximu

文件：292.03 Kbytes 頁(yè)數(shù)：16 Pages

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絲印：ICS87008AGI；Package：TSSOP；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes 頁(yè)數(shù)：16 Pages

IDT

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES ? Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) ? Selectable differential CLK1, nCLK1 or LVCMOS clock input ? CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL ? CLK0 supports the following input types: LVCMOS, LVTTL ? Maximu

文件：292.03 Kbytes 頁(yè)數(shù)：16 Pages

RENESAS

瑞薩

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes 頁(yè)數(shù)：16 Pages

IDT

7.0A, 20V, 0.023 Ohm, Dual N-Channel, 2.5V Specified Power MOSFET

Features ? Ultra Low On-Resistance - rDS(ON) = 0.023?, VGS = 4.5V - rDS(ON) = 0.024?, VGS = 4.0V - rDS(ON) = 0.029?, VGS = 2.5V ? 2.5 Volt Gate Drive Capability ? Gate to Source Protection Diode ? Simulation Models - Temperature Compensated PSPICE? and SABER Electrical Mode

文件：203.38 Kbytes 頁(yè)數(shù)：13 Pages

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